mirror of https://github.com/efabless/caravel.git
289 lines
9.2 KiB
Verilog
289 lines
9.2 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*
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*---------------------------------------------------------------------
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* See gpio_control_block for description. This module is like
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* gpio_contro_block except that it has an additional two management-
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* Soc-facing pins, which are the out_enb line and the output line.
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* If the chip is configured for output with the oeb control
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* register = 1, then the oeb line is controlled by the additional
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* signal from the management SoC. If the oeb control register = 0,
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* then the output is disabled completely. The "io" line is input
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* only in this module.
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*
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*---------------------------------------------------------------------
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*/
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/*
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*---------------------------------------------------------------------
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*
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* This module instantiates a shift register chain that passes through
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* each gpio cell. These are connected end-to-end around the padframe
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* periphery. The purpose is to avoid a massive number of control
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* wires between the digital core and I/O, passing through the user area.
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*
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* See mprj_ctrl.v for the module that registers the data for each
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* I/O and drives the input to the shift register.
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*
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* Modified 7/24/2022 by Tim Edwards
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* Replaced the data delay with a negative edge-triggered flop
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* so that the serial data bit out from the module only changes on
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* the clock half cycle. This avoids the need to fine-tune the clock
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* skew between GPIO blocks.
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*
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* Modified 10/05/2022 by Tim Edwards
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*
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*---------------------------------------------------------------------
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*/
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module gpio_control_block #(
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parameter PAD_CTRL_BITS = 13
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) (
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`ifdef USE_POWER_PINS
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inout vccd,
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inout vssd,
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inout vccd1,
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inout vssd1,
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`endif
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// Power-on defaults
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input [PAD_CTRL_BITS-1:0] gpio_defaults,
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// Management Soc-facing signals
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input resetn, // Global reset, locally propagated
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output resetn_out,
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input serial_clock, // Global clock, locally propatated
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output serial_clock_out,
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input serial_load, // Register load strobe
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output serial_load_out,
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output mgmt_gpio_in, // Management from pad (input only)
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input mgmt_gpio_out, // Management to pad (output only)
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input mgmt_gpio_oeb, // Management to pad (output only)
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// Serial data chain for pad configuration
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input serial_data_in,
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output serial_data_out,
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// User-facing signals
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input user_gpio_out, // User space to pad
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input user_gpio_oeb, // Output enable (user)
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output user_gpio_in, // Pad to user space
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// Pad-facing signals (Pad GPIOv2)
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output pad_gpio_holdover,
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output pad_gpio_slow_sel,
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output pad_gpio_vtrip_sel,
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output pad_gpio_inenb,
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output pad_gpio_ib_mode_sel,
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output pad_gpio_ana_en,
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output pad_gpio_ana_sel,
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output pad_gpio_ana_pol,
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output [2:0] pad_gpio_dm,
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output pad_gpio_outenb,
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output pad_gpio_out,
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input pad_gpio_in,
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// to provide a way to automatically disable/enable output
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// from the outside with needing a conb cell
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output one,
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output zero
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);
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/* Parameters defining the bit offset of each function in the chain */
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localparam MGMT_EN = 0;
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localparam OEB = 1;
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localparam HLDH = 2;
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localparam INP_DIS = 3;
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localparam MOD_SEL = 4;
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localparam AN_EN = 5;
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localparam AN_SEL = 6;
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localparam AN_POL = 7;
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localparam SLOW = 8;
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localparam TRIP = 9;
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localparam DM = 10;
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/* Internally registered signals */
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reg mgmt_ena; // Enable management SoC to access pad
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reg gpio_holdover;
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reg gpio_slow_sel;
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reg gpio_vtrip_sel;
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reg gpio_inenb;
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reg gpio_ib_mode_sel;
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reg gpio_outenb;
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reg [2:0] gpio_dm;
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reg gpio_ana_en;
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reg gpio_ana_sel;
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reg gpio_ana_pol;
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/* Derived output values */
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wire pad_gpio_holdover;
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wire pad_gpio_slow_sel;
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wire pad_gpio_vtrip_sel;
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wire pad_gpio_inenb;
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wire pad_gpio_ib_mode_sel;
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wire pad_gpio_ana_en;
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wire pad_gpio_ana_sel;
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wire pad_gpio_ana_pol;
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wire [2:0] pad_gpio_dm;
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wire pad_gpio_outenb;
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wire pad_gpio_out;
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wire pad_gpio_in;
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wire one_unbuf;
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wire zero_unbuf;
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wire one;
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wire zero;
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wire user_gpio_in;
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wire gpio_logic1;
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reg serial_data_out;
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/* Serial shift for the above (latched) values */
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reg [PAD_CTRL_BITS-1:0] shift_register;
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/* Latch the output on the clock negative edge */
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always @(negedge serial_clock or negedge resetn) begin
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if (resetn == 1'b0) begin
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/* Clear the shift register output */
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serial_data_out <= 1'b0;
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end else begin
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serial_data_out <= shift_register[PAD_CTRL_BITS-1];
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end
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end
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/* Propagate the clock and reset signals so that they aren't wired */
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/* all over the chip, but are just wired between the blocks. */
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assign serial_clock_out = serial_clock;
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assign resetn_out = resetn;
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assign serial_load_out = serial_load;
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always @(posedge serial_clock or negedge resetn) begin
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if (resetn == 1'b0) begin
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/* Clear shift register */
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shift_register <= 'd0;
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end else begin
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/* Shift data in */
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shift_register <= {shift_register[PAD_CTRL_BITS-2:0], serial_data_in};
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end
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end
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always @(posedge serial_load or negedge resetn) begin
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if (resetn == 1'b0) begin
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/* Initial state on reset depends on applied defaults */
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mgmt_ena <= gpio_defaults[MGMT_EN];
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gpio_holdover <= gpio_defaults[HLDH];
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gpio_slow_sel <= gpio_defaults[SLOW];
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gpio_vtrip_sel <= gpio_defaults[TRIP];
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gpio_ib_mode_sel <= gpio_defaults[MOD_SEL];
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gpio_inenb <= gpio_defaults[INP_DIS];
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gpio_outenb <= gpio_defaults[OEB];
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gpio_dm <= gpio_defaults[DM+2:DM];
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gpio_ana_en <= gpio_defaults[AN_EN];
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gpio_ana_sel <= gpio_defaults[AN_SEL];
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gpio_ana_pol <= gpio_defaults[AN_POL];
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end else begin
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/* Load data */
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mgmt_ena <= shift_register[MGMT_EN];
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gpio_outenb <= shift_register[OEB];
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gpio_holdover <= shift_register[HLDH];
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gpio_inenb <= shift_register[INP_DIS];
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gpio_ib_mode_sel <= shift_register[MOD_SEL];
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gpio_ana_en <= shift_register[AN_EN];
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gpio_ana_sel <= shift_register[AN_SEL];
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gpio_ana_pol <= shift_register[AN_POL];
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gpio_slow_sel <= shift_register[SLOW];
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gpio_vtrip_sel <= shift_register[TRIP];
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gpio_dm <= shift_register[DM+2:DM];
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end
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end
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/* These pad configuration signals are static and do not change */
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/* after setup. */
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assign pad_gpio_holdover = gpio_holdover;
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assign pad_gpio_slow_sel = gpio_slow_sel;
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assign pad_gpio_vtrip_sel = gpio_vtrip_sel;
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assign pad_gpio_ib_mode_sel = gpio_ib_mode_sel;
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assign pad_gpio_ana_en = gpio_ana_en;
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assign pad_gpio_ana_sel = gpio_ana_sel;
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assign pad_gpio_ana_pol = gpio_ana_pol;
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assign pad_gpio_dm = gpio_dm;
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assign pad_gpio_inenb = gpio_inenb;
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/* Implement pad control behavior depending on state of mgmt_ena */
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/* The pad value always goes back to the housekeeping module */
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assign mgmt_gpio_in = pad_gpio_in;
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/* For 2-wire interfaces, the mgmt_gpio_oeb line is tied high at */
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/* the control block. In this case, the output enable state is */
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/* determined by the OEB configuration bit. */
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assign pad_gpio_outenb = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ?
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gpio_outenb : 1'b0) : user_gpio_oeb;
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/* For 2-wire interfaces, if the pad is configured for pull-up or */
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/* pull-down, drive the output value locally to achieve the */
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/* expected pull. */
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assign pad_gpio_out = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ?
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((gpio_dm[2:1] == 2'b01) ? ~gpio_dm[0] : mgmt_gpio_out) :
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mgmt_gpio_out) : user_gpio_out;
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/* Buffer user_gpio_in with an enable that is set by the user domain vccd */
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gpio_logic_high gpio_logic_high (
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`ifdef USE_POWER_PINS
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.vccd1(vccd1),
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.vssd1(vssd1),
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`endif
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.gpio_logic1(gpio_logic1)
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);
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/* If user project area is powered down, zero the pad input value */
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/* going to the user project. */
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assign user_gpio_in = pad_gpio_in & gpio_logic1;
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(* keep *)
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sky130_fd_sc_hd__macro_sparecell spare_cell (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd)
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`endif
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);
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sky130_fd_sc_hd__conb_1 const_source (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.HI(one_unbuf),
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.LO(zero_unbuf)
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);
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assign zero = zero_unbuf;
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assign one = one_unbuf;
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endmodule
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`default_nettype wire
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