mirror of https://github.com/efabless/caravel.git
489 lines
15 KiB
Verilog
489 lines
15 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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// `default_nettype none
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/* Alternative padframe that removes the GPIO from the top row, */
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/* replacing them with un-overlaid power pads which have a */
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/* direct connection from pad to core. */
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/* For convenience, all of the original GPIO signals remain */
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/* defined in the I/O list, although some are not connected. */
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/* ANALOG_PADS_1 = Number of GPIO pads in the user 1 section */
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/* that are replaced by straight-through analog */
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/* ANALOG_PADS_2 = Number of GPIO pads in the user 2 section */
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/* that are replaced by straight-through analog */
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module chip_io_alt #(
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parameter ANALOG_PADS_1 = 5,
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parameter ANALOG_PADS_2 = 6
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) (
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// Package Pins
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inout vddio_pad, // Common padframe/ESD supply
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inout vddio_pad2, // Common padframe/ESD supply
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inout vssio_pad, // Common padframe/ESD ground
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inout vssio_pad2, // Common padframe/ESD ground
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inout vccd_pad, // Common 1.8V supply
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inout vssd_pad, // Common digital ground
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inout vdda_pad, // Management analog 3.3V supply
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inout vssa_pad, // Management analog ground
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inout vdda1_pad, // User area 1 3.3V supply
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inout vdda1_pad2, // User area 1 3.3V supply
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inout vdda2_pad, // User area 2 3.3V supply
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inout vssa1_pad, // User area 1 analog ground
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inout vssa1_pad2, // User area 1 analog ground
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inout vssa2_pad, // User area 2 analog ground
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inout vccd1_pad, // User area 1 1.8V supply
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inout vccd2_pad, // User area 2 1.8V supply
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inout vssd1_pad, // User area 1 digital ground
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inout vssd2_pad, // User area 2 digital ground
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// Core Side
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inout vddio, // Common padframe/ESD supply
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inout vssio, // Common padframe/ESD ground
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inout vccd, // Common 1.8V supply
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inout vssd, // Common digital ground
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inout vdda, // Management analog 3.3V supply
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inout vssa, // Management analog ground
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8V supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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inout gpio,
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input clock,
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input resetb,
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output flash_csb,
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output flash_clk,
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inout flash_io0,
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inout flash_io1,
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// Chip Core Interface
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input porb_h,
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input por,
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output resetb_core_h,
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output clock_core,
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input gpio_out_core,
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output gpio_in_core,
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input gpio_mode0_core,
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input gpio_mode1_core,
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input gpio_outenb_core,
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input gpio_inenb_core,
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input flash_csb_core,
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input flash_clk_core,
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input flash_csb_oeb_core,
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input flash_clk_oeb_core,
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input flash_io0_oeb_core,
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input flash_io1_oeb_core,
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input flash_csb_ieb_core,
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input flash_clk_ieb_core,
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input flash_io0_ieb_core,
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input flash_io1_ieb_core,
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input flash_io0_do_core,
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input flash_io1_do_core,
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output flash_io0_di_core,
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output flash_io1_di_core,
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// User project IOs
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// mprj_io is defined for all pads, both digital and analog
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inout [`MPRJ_IO_PADS-1:0] mprj_io,
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// The section below is for the digital pads only.
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_out,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_oeb,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_inp_dis,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_ib_mode_sel,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_vtrip_sel,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_slow_sel,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_holdover,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_analog_en,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_analog_sel,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_analog_pol,
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input [(`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2)*3-1:0] mprj_io_dm,
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output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in,
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output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in_3v3,
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input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_one,
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// User project direct access to gpio pad connections for analog
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// "analog" connects to the "esd_0" pin of the GPIO pad, and
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// "analog_noesd" connects to the "noesd" pin of the GPIO pad.
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// User side 1: Connects to all but the first 7 pads;
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// User side 2: Connects to all but the last 2 pads
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inout [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-10:0] mprj_gpio_analog,
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inout [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-10:0] mprj_gpio_noesd,
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// Core connections for the analog signals
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inout [ANALOG_PADS_1+ANALOG_PADS_2-1:0] mprj_analog,
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// These are clamp connections for the clamps in the analog cells, if
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// they are used for power supplies.
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// User side 1: Connects to
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input [2:0] mprj_clamp_high,
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input [2:0] mprj_clamp_low
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);
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wire analog_a, analog_b;
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wire vddio_q, vssio_q;
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// To be considered: Master hold signal on all user pads (?)
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// For now, set holdh_n to 1 internally (NOTE: This is in the
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// VDDIO 3.3V domain) and setting enh to porb_h.
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_enh;
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assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
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// Instantiate power and ground pads for management domain
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// 12 pads: vddio, vssio, vdda, vssa, vccd, vssd
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// One each HV and LV clamp.
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// HV clamps connect between one HV power rail and one ground
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// LV clamps have two clamps connecting between any two LV power
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// rails and grounds, and one back-to-back diode which connects
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// between the first LV clamp ground and any other ground.
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sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDIO_PAD(vddio_pad)
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`endif
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);
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// lies in user area 2
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sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDIO_PAD(vddio_pad2)
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`endif
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);
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sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDA_PAD(vdda_pad)
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`endif
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);
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sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VCCD_PAD(vccd_pad)
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`endif
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);
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sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSIO_PAD(vssio_pad)
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`endif
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);
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sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSIO_PAD(vssio_pad2)
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`endif
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);
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sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSA_PAD(vssa_pad)
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`endif
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);
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sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSD_PAD(vssd_pad)
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`endif
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);
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// Instantiate power and ground pads for user 1 domain
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// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
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sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDA_PAD(vdda1_pad)
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`endif
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);
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sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDA_PAD(vdda1_pad2)
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`endif
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);
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sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
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`USER1_ABUTMENT_PINS
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.VCCD1(vccd1),
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.VSSD1(vssd1),
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`ifndef TOP_ROUTING
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.VCCD_PAD(vccd1_pad)
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`endif
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);
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sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSA_PAD(vssa1_pad)
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`endif
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);
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sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSA_PAD(vssa1_pad2)
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`endif
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);
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sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
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`USER1_ABUTMENT_PINS
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.VCCD1(vccd1),
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.VSSD1(vssd1),
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`ifndef TOP_ROUTING
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.VSSD_PAD(vssd1_pad)
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`endif
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);
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// Instantiate power and ground pads for user 2 domain
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// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
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sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDA_PAD(vdda2_pad)
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`endif
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);
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sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
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`USER2_ABUTMENT_PINS
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.VCCD1(vccd2),
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.VSSD1(vssd2),
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`ifndef TOP_ROUTING
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.VCCD_PAD(vccd2_pad)
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`endif
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);
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sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSA_PAD(vssa2_pad)
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`endif
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);
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sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
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`USER2_ABUTMENT_PINS
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.VCCD1(vccd2),
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.VSSD1(vssd2),
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`ifndef TOP_ROUTING
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.VSSD_PAD(vssd2_pad)
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`endif
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);
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// Instantiate analog pads in user area 1 using the custom analog pad
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sky130_ef_io__analog_pad user1_analog_pad [ANALOG_PADS_1-2:0] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.P_PAD(mprj_io[`MPRJ_IO_PADS_1-2:`MPRJ_IO_PADS_1-ANALOG_PADS_1]),
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`endif
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.P_CORE(mprj_analog[ANALOG_PADS_1-2:0])
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);
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// Last analog pad is a power pad, to provide a clamp resource.
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sky130_ef_io__top_power_hvc user1_analog_pad_with_clamp (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.P_PAD(mprj_io[`MPRJ_IO_PADS_1-1]),
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`endif
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`HVCLAMP_PINS(mprj_clamp_high[0],
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mprj_clamp_low[0]),
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.P_CORE(mprj_analog[ANALOG_PADS_1-1])
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);
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// Instantiate analog pads in user area 2 using the custom analog pad.
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sky130_ef_io__analog_pad user2_analog_pad [ANALOG_PADS_2-3:0] (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.P_PAD(mprj_io[`MPRJ_IO_PADS_1+ANALOG_PADS_2-1:`MPRJ_IO_PADS_1+2]),
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`endif
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.P_CORE(mprj_analog[ANALOG_PADS_2+ANALOG_PADS_1-1:ANALOG_PADS_1+2])
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);
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// Last two analog pads are power pads, to provide clamp resources.
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sky130_ef_io__top_power_hvc user2_analog_pad_with_clamp [1:0] (
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`ifndef TOP_ROUTING
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.P_PAD(mprj_io[`MPRJ_IO_PADS_1+1:`MPRJ_IO_PADS_1]),
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`endif
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`HVCLAMP_PINS(mprj_clamp_high[2:1], mprj_clamp_low[2:1]),
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.P_CORE(mprj_analog[`ANALOG_PADS_1+1:ANALOG_PADS_1])
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);
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wire [2:0] dm_all =
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{gpio_mode1_core, gpio_mode1_core, gpio_mode0_core};
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wire[2:0] flash_io0_mode =
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{flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core};
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wire[2:0] flash_io1_mode =
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{flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core};
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wire [6:0] vccd_const_one; // Constant value for management pins
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wire [6:0] vssd_const_zero; // Constant value for management pins
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constant_block constant_value_inst [6:0] (
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.vccd(vccd),
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.vssd(vssd),
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.one(vccd_const_one),
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.zero(vssd_const_zero)
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);
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// Management clock input pad
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`INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]);
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// Management GPIO pad
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`INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all);
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// Management Flash SPI pads
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`INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one[2], vssd_const_zero[2], flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
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`INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one[3], vssd_const_zero[3], flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
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`OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one[4], vssd_const_zero[4], flash_csb_oeb_core);
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`OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one[5], vssd_const_zero[5], flash_clk_oeb_core);
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// NOTE: The analog_out pad from the raven chip has been replaced by
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// the digital reset input resetb on caravel due to the lack of an on-board
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// power-on-reset circuit. The XRES pad is used for providing a glitch-
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// free reset.
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wire xresloop;
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wire xres_zero_loop
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sky130_fd_io__top_xres4v2 resetb_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.PAD(resetb),
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`endif
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.TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
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.TIE_HI_ESD(),
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.TIE_LO_ESD(xres_zero_loop),
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.PAD_A_ESD_H(xresloop),
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.XRES_H_N(resetb_core_h),
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.DISABLE_PULLUP_H(xres_zero_loop), // 0 = enable pull-up on reset pad
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.ENABLE_H(porb_h), // Power-on-reset
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.EN_VDDIO_SIG_H(xres_zero_loop), // No idea.
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.INP_SEL_H(xres_zero_loop), // 1 = use filt_in_h else filter the pad input
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.FILT_IN_H(xres_zero_loop), // Alternate input for glitch filter
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.PULLUP_H(xres_zero_loop), // Pullup connection for alternate filter input
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.ENABLE_VDDIO(vccd_const_one[6])
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);
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// Corner cells (These are overlay cells; it is not clear what is normally
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// supposed to go under them.)
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sky130_ef_io__corner_pad mgmt_corner [1:0] (
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`ifndef TOP_ROUTING
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.VSSIO(vssio),
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.VDDIO(vddio),
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.VDDIO_Q(vddio_q),
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.VSSIO_Q(vssio_q),
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.AMUXBUS_A(analog_a),
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.AMUXBUS_B(analog_b),
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.VSSD(vssd),
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.VSSA(vssa),
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.VSWITCH(vddio),
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.VDDA(vdda),
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.VCCD(vccd),
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.VCCHIB(vccd)
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`endif
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);
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|
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sky130_ef_io__corner_pad user1_corner (
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`ifndef TOP_ROUTING
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.VSSIO(vssio),
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.VDDIO(vddio),
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.VDDIO_Q(vddio_q),
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.VSSIO_Q(vssio_q),
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.AMUXBUS_A(analog_a),
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.AMUXBUS_B(analog_b),
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.VSSD(vssd),
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.VSSA(vssa1),
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.VSWITCH(vddio),
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.VDDA(vdda1),
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.VCCD(vccd),
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.VCCHIB(vccd)
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`endif
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);
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sky130_ef_io__corner_pad user2_corner (
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|
`ifndef TOP_ROUTING
|
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.VSSIO(vssio),
|
|
.VDDIO(vddio),
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|
.VDDIO_Q(vddio_q),
|
|
.VSSIO_Q(vssio_q),
|
|
.AMUXBUS_A(analog_a),
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.AMUXBUS_B(analog_b),
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.VSSD(vssd),
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|
.VSSA(vssa2),
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|
.VSWITCH(vddio),
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|
.VDDA(vdda2),
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|
.VCCD(vccd),
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|
.VCCHIB(vccd)
|
|
`endif
|
|
);
|
|
|
|
mprj_io #(
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.AREA1PADS(`MPRJ_IO_PADS_1 - ANALOG_PADS_1),
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.TOTAL_PADS(`MPRJ_IO_PADS - ANALOG_PADS_1 - ANALOG_PADS_2)
|
|
) mprj_pads (
|
|
.vddio(vddio),
|
|
.vssio(vssio),
|
|
.vccd(vccd),
|
|
.vssd(vssd),
|
|
.vdda1(vdda1),
|
|
.vdda2(vdda2),
|
|
.vssa1(vssa1),
|
|
.vssa2(vssa2),
|
|
.vddio_q(vddio_q),
|
|
.vssio_q(vssio_q),
|
|
.analog_a(analog_a),
|
|
.analog_b(analog_b),
|
|
.porb_h(porb_h),
|
|
.vccd_conb(mprj_io_one),
|
|
|
|
.io({mprj_io[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS_1+ANALOG_PADS_2],
|
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mprj_io[`MPRJ_IO_PADS_1-ANALOG_PADS_1-1:0]}),
|
|
.io_out(mprj_io_out),
|
|
.oeb(mprj_io_oeb),
|
|
.enh(mprj_io_enh),
|
|
.inp_dis(mprj_io_inp_dis),
|
|
.ib_mode_sel(mprj_io_ib_mode_sel),
|
|
.vtrip_sel(mprj_io_vtrip_sel),
|
|
.holdover(mprj_io_holdover),
|
|
.slow_sel(mprj_io_slow_sel),
|
|
.analog_en(mprj_io_analog_en),
|
|
.analog_sel(mprj_io_analog_sel),
|
|
.analog_pol(mprj_io_analog_pol),
|
|
.dm(mprj_io_dm),
|
|
.io_in(mprj_io_in),
|
|
.io_in_3v3(mprj_io_in_3v3),
|
|
.analog_io(mprj_gpio_analog),
|
|
.analog_noesd_io(mprj_gpio_noesd)
|
|
);
|
|
|
|
endmodule
|
|
// `default_nettype wire
|