mirror of https://github.com/efabless/caravel.git
35 lines
2.3 KiB
Plaintext
35 lines
2.3 KiB
Plaintext
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
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87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
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684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
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b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
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462e675b1c3d5949856b5d8b7b893ffa5a012f79 verilog/rtl/caravan.v
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a2d65c149e87a9892bce34281e5322c01ce50119 verilog/rtl/caravan_netlists.v
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a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
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bc32bfb9b30f358219531ccab71421aec21d1300 verilog/rtl/caravel.v
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2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
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3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
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fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v
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8a4f1bd4eb40367c3ca8df76df6e1423a8271461 verilog/rtl/chip_io_alt.v
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126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
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941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
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36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
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ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
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2b8a0d04b8f7214a5205aade7ec074fe32dbb44e verilog/rtl/gpio_control_block.v
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9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
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32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
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5cecb651a1f7c36d7ae3c4bbca3950ace4186cd5 verilog/rtl/housekeeping.v
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3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
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ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
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3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
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9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
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d71adbc70dbb0ed879d3b75419bd807c866a9680 verilog/rtl/mprj_io.v
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3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
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4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v
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669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
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6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v
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1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v
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8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
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c94f7ed5aa311f005513ace344991c8e6d3d19f5 scripts/set_user_id.py
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98168b1fb6f80b196f9a05e725ec6ad99bc57ac6 scripts/generate_fill.py
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3210e724c6dc99563af780ff1778fada5b432604 scripts/compositor.py
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