caravel/verilog
kareem 59743f4832 change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
..
dv added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list 2022-10-10 06:23:47 -07:00
gl change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
rtl change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00