mirror of https://github.com/efabless/caravel.git
33 lines
825 B
Verilog
33 lines
825 B
Verilog
module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H, XRES_H_N, TIE_HI_ESD, TIE_LO_ESD,
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AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H,
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DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO
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,VCCD, VCCHIB, VDDA, VDDIO,VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH
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);
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output XRES_H_N;
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inout AMUXBUS_A;
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inout AMUXBUS_B;
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inout PAD;
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input DISABLE_PULLUP_H;
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input ENABLE_H;
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input EN_VDDIO_SIG_H;
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input INP_SEL_H;
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input FILT_IN_H;
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inout PULLUP_H;
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input ENABLE_VDDIO;
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input VCCD;
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input VCCHIB;
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input VDDA;
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input VDDIO;
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input VDDIO_Q;
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input VSSA;
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input VSSD;
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input VSSIO;
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input VSSIO_Q;
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input VSWITCH;
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inout PAD_A_ESD_H;
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output TIE_HI_ESD;
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output TIE_LO_ESD;
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inout TIE_WEAK_HI_H;
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endmodule
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