mirror of https://github.com/efabless/caravel.git
134 lines
4.0 KiB
Tcl
134 lines
4.0 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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# User config
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set script_dir [file dirname [file normalize [info script]]]
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set ::env(DESIGN_NAME) caravan
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set ::env(STD_CELL_LIBRARY_OPT) "sky130_fd_sc_hd"
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set verilog_root $script_dir/../../verilog/
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set lef_root $script_dir/../../lef/
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set gds_root $script_dir/../../gds/
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set mgmt_area_verilog_root $script_dir/../../../caravel_pico/verilog/
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set mgmt_area_lef_root $script_dir/../../../caravel_pico/lef/
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set mgmt_area_gds_root $script_dir/../../../caravel_pico/gds/
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# Change if needed
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set ::env(VERILOG_FILES) "\
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$verilog_root/rtl/user_defines.v \
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$verilog_root/rtl/caravan.v"
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$verilog_root/rtl/defines.v \
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$verilog_root/rtl/pads.v \
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$verilog_root/rtl/chip_io_alt.v \
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$verilog_root/rtl/__user_analog_project_wrapper.v \
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$verilog_root/rtl/mgmt_protect.v \
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$verilog_root/rtl/gpio_defaults_block.v \
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$verilog_root/rtl/gpio_control_block.v \
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$verilog_root/rtl/user_id_programming.v \
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$verilog_root/rtl/housekeeping.v \
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$verilog_root/rtl/digital_pll.v \
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$verilog_root/rtl/caravel_clocking.v \
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$verilog_root/rtl/simple_por.v\
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$verilog_root/rtl/xres_buf.v \
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$mgmt_area_verilog_root/rtl/mgmt_core_wrapper.v \
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"
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set ::env(EXTRA_LEFS) "\
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$lef_root/chip_io_alt.lef \
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$lef_root/user_analog_project_wrapper.lef \
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$lef_root/mgmt_protect.lef \
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$lef_root/gpio_control_block.lef \
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$lef_root/gpio_defaults_block.lef \
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$lef_root/user_id_programming.lef \
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$lef_root/housekeeping.lef \
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$lef_root/digital_pll.lef \
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$lef_root/caravel_clocking.lef \
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$lef_root/simple_por.lef\
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$lef_root/xres_buf.lef\
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$mgmt_area_lef_root/mgmt_core_wrapper.lef \
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"
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set ::env(EXTRA_GDS_FILES) "\
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$gds_root/chip_io_alt.gds \
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$gds_root/user_analog_project_wrapper.gds \
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$gds_root/mgmt_protect.gds \
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$gds_root/gpio_control_block.gds \
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$gds_root/gpio_defaults_block.gds \
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$gds_root/user_id_programming.gds \
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$gds_root/housekeeping.gds \
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$gds_root/digital_pll.gds \
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$gds_root/caravel_clocking.gds \
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$gds_root/simple_por.gds\
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$gds_root/xres_buf.gds\
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$mgmt_area_gds_root/mgmt_core_wrapper.gds \
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"
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# # !!!
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# if { [info exists ::env(LVS_RUN_DIR)] || [info exists ::env(CONNECTIVITY_RUN)] } {
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# # if running to get a full floorplan, need the original pads due to
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# # missing pins in the abstracted version
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# set ::env(GPIO_PADS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lef/s8iom0s8/*.lef"]
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# }
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set ::env(SYNTH_TOP_LEVEL) 1
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set ::env(SYNTH_FLAT_TOP) 1
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set ::env(LEC_ENABLE) 0
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set ::env(FP_SIZING) absolute
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set fd [open "$script_dir/../chip_dimensions.txt" "r"]
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set ::env(DIE_AREA) [read $fd]
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close $fd
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set ::env(CELL_PAD) 0
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(DIODE_INSERTION_STRATEGY) 0
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set ::env(GLB_RT_ALLOW_CONGESTION) 1
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set ::env(GLB_RT_OVERFLOW_ITERS) 50
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set ::env(GLB_RT_TILES) 30
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set ::env(GLB_RT_MINLAYER) 2
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set ::env(GLB_RT_MAXLAYER) 6
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set ::env(GLB_RT_ADJUSTMENT) "0"
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set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
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set ::env(GLB_RT_L2_ADJUSTMENT) "0.1"
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set ::env(GLB_RT_L3_ADJUSTMENT) "0.15"
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set ::env(GLB_RT_L4_ADJUSTMENT) "0.15"
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set ::env(GLB_RT_L5_ADJUSTMENT) "0.15"
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set ::env(GLB_RT_L6_ADJUSTMENT) "0"
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# set ::env(ROUTING_OPT_ITERS) 7
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# set ::env(GLB_RT_UNIDIRECTIONAL) 0
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set ::env(FILL_INSERTION) 0
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# DON'T PUT CELLS ON THE TOP LEVEL
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set ::env(LVS_INSERT_POWER_PINS) 0
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set ::env(MAGIC_GENERATE_LEF) 0
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set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0 |