mirror of https://github.com/efabless/caravel.git
248 lines
5.3 KiB
Plaintext
248 lines
5.3 KiB
Plaintext
VERSION 5.7 ;
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NOWIREEXTENSIONATPIN ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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MACRO caravel_clocking
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CLASS BLOCK ;
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FOREIGN caravel_clocking ;
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ORIGIN 0.000 0.000 ;
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SIZE 100.000 BY 100.000 ;
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PIN VGND
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DIRECTION INOUT ;
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USE GROUND ;
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PORT
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LAYER met4 ;
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RECT 15.500 2.480 17.100 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 31.000 2.480 32.600 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 46.500 2.480 48.100 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 62.000 2.480 63.600 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 77.500 2.480 79.100 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 93.000 2.480 94.600 92.720 ;
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END
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END VGND
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PIN VPWR
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DIRECTION INOUT ;
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USE POWER ;
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PORT
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LAYER met4 ;
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RECT 7.750 2.480 9.350 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 23.250 2.480 24.850 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 38.750 2.480 40.350 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 54.250 2.480 55.850 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 69.750 2.480 71.350 92.720 ;
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END
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PORT
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LAYER met4 ;
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RECT 85.250 2.480 86.850 92.720 ;
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END
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END VPWR
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PIN core_clk
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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ANTENNADIFFAREA 0.340600 ;
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PORT
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LAYER met2 ;
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RECT 35.510 96.000 35.790 100.000 ;
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END
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END core_clk
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PIN ext_clk
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met2 ;
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RECT 21.250 96.000 21.530 100.000 ;
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END
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END ext_clk
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PIN ext_clk_sel
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met3 ;
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RECT 96.000 6.840 100.000 7.440 ;
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END
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END ext_clk_sel
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PIN ext_reset
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met3 ;
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RECT 96.000 92.520 100.000 93.120 ;
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END
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END ext_reset
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PIN pll_clk
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met2 ;
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RECT 78.290 96.000 78.570 100.000 ;
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END
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END pll_clk
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PIN pll_clk90
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met2 ;
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RECT 92.550 96.000 92.830 100.000 ;
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END
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END pll_clk90
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PIN porb
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met3 ;
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RECT 0.000 49.680 4.000 50.280 ;
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END
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END porb
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PIN resetb
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met2 ;
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RECT 6.990 96.000 7.270 100.000 ;
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END
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END resetb
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PIN resetb_sync
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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ANTENNADIFFAREA 0.340600 ;
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PORT
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LAYER met2 ;
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RECT 64.030 96.000 64.310 100.000 ;
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END
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END resetb_sync
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PIN sel2[0]
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met3 ;
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RECT 96.000 55.800 100.000 56.400 ;
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END
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END sel2[0]
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PIN sel2[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met3 ;
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RECT 96.000 68.040 100.000 68.640 ;
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END
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END sel2[1]
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PIN sel2[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met3 ;
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RECT 96.000 80.280 100.000 80.880 ;
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END
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END sel2[2]
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PIN sel[0]
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met3 ;
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RECT 96.000 19.080 100.000 19.680 ;
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END
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END sel[0]
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PIN sel[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met3 ;
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RECT 96.000 31.320 100.000 31.920 ;
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END
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END sel[1]
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PIN sel[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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ANTENNAGATEAREA 0.126000 ;
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PORT
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LAYER met3 ;
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RECT 96.000 43.560 100.000 44.160 ;
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END
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END sel[2]
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PIN user_clk
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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ANTENNADIFFAREA 0.340600 ;
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PORT
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LAYER met2 ;
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RECT 49.770 96.000 50.050 100.000 ;
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END
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END user_clk
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OBS
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LAYER li1 ;
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RECT 0.920 2.635 94.300 92.565 ;
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LAYER met1 ;
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RECT 0.920 2.480 95.610 92.720 ;
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LAYER met2 ;
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RECT 4.240 95.720 6.710 96.290 ;
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RECT 7.550 95.720 20.970 96.290 ;
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RECT 21.810 95.720 35.230 96.290 ;
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RECT 36.070 95.720 49.490 96.290 ;
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RECT 50.330 95.720 63.750 96.290 ;
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RECT 64.590 95.720 78.010 96.290 ;
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RECT 78.850 95.720 92.270 96.290 ;
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RECT 93.110 95.720 95.590 96.290 ;
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RECT 4.240 2.535 95.590 95.720 ;
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LAYER met3 ;
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RECT 4.000 92.120 95.600 92.985 ;
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RECT 4.000 81.280 96.000 92.120 ;
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RECT 4.000 79.880 95.600 81.280 ;
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RECT 4.000 69.040 96.000 79.880 ;
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RECT 4.000 67.640 95.600 69.040 ;
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RECT 4.000 56.800 96.000 67.640 ;
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RECT 4.000 55.400 95.600 56.800 ;
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RECT 4.000 50.680 96.000 55.400 ;
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RECT 4.400 49.280 96.000 50.680 ;
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RECT 4.000 44.560 96.000 49.280 ;
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RECT 4.000 43.160 95.600 44.560 ;
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RECT 4.000 32.320 96.000 43.160 ;
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RECT 4.000 30.920 95.600 32.320 ;
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RECT 4.000 20.080 96.000 30.920 ;
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RECT 4.000 18.680 95.600 20.080 ;
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RECT 4.000 7.840 96.000 18.680 ;
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RECT 4.000 6.440 95.600 7.840 ;
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RECT 4.000 2.555 96.000 6.440 ;
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END
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END caravel_clocking
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END LIBRARY
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