Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals ... being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).		2022-10-16 12:49:44 -04:00
..
dv	fix script to not create directory annotation_logs	2022-10-15 02:54:35 -07:00
gl	add mgmt_protect views and openlane files	2022-10-16 03:14:55 -07:00
rtl	Once again. . . Rewrote the RTL verilog so that only signals	2022-10-16 12:49:44 -04:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00