mirror of https://github.com/efabless/caravel.git
136 lines
3.9 KiB
Tcl
136 lines
3.9 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set ::env(DESIGN_NAME) mgmt_protect
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set ::env(ROUTING_CORES) 24
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set ::env(DESIGN_IS_CORE) 1
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set ::env(PDK) "sky130A"
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set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
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set ::env(BASE_SDC_FILE) [glob $::env(DESIGN_DIR)/base.sdc]
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# set ::env(RUN_KLAYOUT) 1
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# virtual clock
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set ::env(CLOCK_PERIOD) 8
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set ::env(CLOCK_PORT) ""
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# Synthesis
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set ::env(SYNTH_STRATEGY) "AREA 0"
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
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set ::env(CLOCK_TREE_SYNTH) 0
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## Floorplan
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set ::env(FP_SIZING) absolute
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# set ::env(DIE_AREA) "0 0 1100 160" 320um to the left
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set ::env(DIE_AREA) "0 0 1900 160"
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set ::env(FP_PIN_ORDER_CFG) [glob $::env(DESIGN_DIR)/pin_order.cfg]
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set ::env(FP_PDN_VERTICAL_HALO) 10
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set ::env(FP_PDN_HORIZONTAL_HALO) 10
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set ::env(FP_IO_MIN_DISTANCE) 5
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set ::env(BOTTOM_MARGIN_MULT) 2
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set ::env(TOP_MARGIN_MULT) 2
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set ::env(LEFT_MARGIN_MULT) 12
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set ::env(RIGHT_MARGIN_MULT) 12
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set ::env(FP_IO_VEXTEND) 2
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set ::env(FP_IO_HEXTEND) 2
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# set ::env(CELL_PAD) 0
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## PDN
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set ::env(PDN_CFG) [glob $::env(DESIGN_DIR)/pdn.tcl]
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set ::env(FP_PDN_UPPER_LAYER) met4
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set ::env(VDD_NETS) "vccd vccd1 vccd2 vdda1 vdda2"
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set ::env(GND_NETS) "vssd vssd1 vssd2 vssa1 vssa2"
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set ::env(FP_PDN_MACRO_HOOKS) "\
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mprj_logic_high_inst vccd1 vssd1 vccd1 vssd1, \
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mprj2_logic_high_inst vccd2 vssd2 vccd2 vssd2, \
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powergood_check vccd vssd vccd vssd, \
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powergood_check vdda1 vssa1 vdda1 vssa1, \
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powergood_check vdda2 vssa2 vdda2 vssa2"
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set ::env(FP_PDN_SKIPTRIM) 0
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## Placement
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set ::env(PL_TARGET_DENSITY) 0.11
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
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set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 25
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## Routing
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set ::env(RT_MIN_LAYER) "met1"
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set ::env(RT_MAX_LAYER) "met4"
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set ::env(GRT_ADJUSTMENT) 0.05
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set ::env(GRT_OVERFLOW_ITERS) 250
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set ::env(GRT_ALLOW_CONGESTION) 0
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
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# set ::env(GLB_RT_OBS) "\
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# met4 390.000 5.26500 414.00 152.68000,\
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# met4 465.0000 5.17000 487.00 153.09000,\
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# met4 540.0000 5.03500 563.0000 152.73000,\
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# met4 691.0000 4.85500 713.0000 152.55000,\
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# met4 766.0000 4.88500 788.0000 152.58000,\
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# met4 841.0000 5.04500 864.0000 152.74000,\
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# met4 916.0000 5.35500 946.0000 153.46500,\
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# met4 992.0000 5.20000 1006.0000 152.56000,\
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# met4 1066.0000 4.90000 1096.0000 153.01000,\
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# met4 612.0000 5.26500 638.0000 153.08000,\
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# met4 990.00000 5.17000 1022.000 153.39500"
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# set ::env(GRT_OBS) "met5 0 0 1900 160"
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) 4
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## Internal Macros
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set ::env(MACRO_PLACEMENT_CFG) [glob $::env(DESIGN_DIR)/macro_placement.cfg]
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set ::env(VERILOG_FILES_BLACKBOX) [glob $::env(DESIGN_DIR)/macros/verilog/*.v]
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set ::env(EXTRA_LEFS) [glob $::env(DESIGN_DIR)/macros/lef/*.lef]
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set ::env(EXTRA_GDS_FILES) [glob $::env(DESIGN_DIR)/macros/gds/*.gds]
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## SIGNOFF
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# set ::env(PRIMARY_SIGNOFF_TOOL) "klayout"
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## DRC
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set ::env(QUIT_ON_MAGIC_DRC) 0
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set ::env(KLAYOUT_DRC_KLAYOUT_GDS) 1
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## LVS
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set ::env(QUIT_ON_LVS_ERROR) 0
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set ::env(MAGIC_EXT_USE_GDS) 0
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# mprj_dat_i_user
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# mprj_ack_i_user
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# user_irq_core
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# set ::env(DONT_TOUCH_PORTS) "la_data_out_core\[*\] mprj_ack_i_user mprj_dat_i_user\[*\] user_irq_core\[*\]"
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set ::env(RSZ_DONT_TOUCH_RX) {la_data_out_core\[.*\]|mprj_ack_i_user|mprj_dat_i_user\[.*\]|user_irq_core\[.*\]}
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