mirror of https://github.com/efabless/caravel.git
55 lines
2.5 KiB
Plaintext
55 lines
2.5 KiB
Plaintext
CVC: Circuit Validation Check Version 1.1.0
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CVC: Log output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt
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CVC: Error output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt.error.gz
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CVC: Debug output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt.debug.gz
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CVC: Start: Thu Oct 13 17:51:27 2022
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Using the following parameters for CVC (Circuit Validation Check) from /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/cvcrc
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CVC_TOP = 'caravel_clocking'
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CVC_NETLIST = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/caravel_clocking.cdl'
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CVC_MODE = 'caravel_clocking'
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CVC_MODEL_FILE = '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/models'
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CVC_POWER_FILE = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/caravel_clocking.power'
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CVC_FUSE_FILE = ''
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CVC_REPORT_FILE = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt'
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CVC_REPORT_TITLE = 'CVC $CVC_TOP'
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CVC_CIRCUIT_ERROR_LIMIT = '100'
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CVC_SEARCH_LIMIT = '100'
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CVC_LEAK_LIMIT = '0.0002'
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CVC_SOI = 'false'
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CVC_SCRC = 'false'
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CVC_VTH_GATES = 'false'
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CVC_MIN_VTH_GATES = 'false'
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CVC_IGNORE_VTH_FLOATING = 'false'
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CVC_IGNORE_NO_LEAK_FLOATING = 'false'
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CVC_LEAK_OVERVOLTAGE = 'true'
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CVC_LOGIC_DIODES = 'false'
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CVC_ANALOG_GATES = 'true'
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CVC_BACKUP_RESULTS = 'false'
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CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
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CVC_SHORT_ERROR_THRESHOLD = '0'
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CVC_BIAS_ERROR_THRESHOLD = '0'
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CVC_FORWARD_ERROR_THRESHOLD = '0'
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CVC_FLOATING_ERROR_THRESHOLD = '0'
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CVC_GATE_ERROR_THRESHOLD = '0'
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CVC_LEAK?_ERROR_THRESHOLD = '0'
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CVC_EXPECTED_ERROR_THRESHOLD = '0'
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CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
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CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
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CVC_CELL_ERROR_LIMIT_FILE = ''
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CVC_CELL_CHECKSUM_FILE = ''
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CVC_LARGE_CIRCUIT_SIZE = '10000000'
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CVC_NET_CHECK_FILE = ''
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CVC_MODEL_CHECK_FILE = ''
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End of parameters
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CVC: Reading device model settings...
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CVC: Reading power settings...
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CVC: Parsing netlist /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/caravel_clocking.cdl
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Cdl fixed data size 26808
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Usage CDL: Time: 0 Memory: 7052 I/O: 8 Swap: 0
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CVC: Counting and linking...
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Fatal error:could not find subcircuit: XFILLER_0_14(sky130_ef_sc_hd__decap_12) in caravel_clocking
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