riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
caravel/verilog/rtl/user_id_textblock.v

3 lines
39 B
Verilog
Raw Blame History

module user_id_textblock ();
endmodule
Reference in New Issue View Git Blame Copy Permalink