mirror of https://github.com/efabless/caravel.git
137 lines
7.9 KiB
Tcl
137 lines
7.9 KiB
Tcl
set ::env(WB_CLK_PERIOD) 25
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set ::env(SCK_CLK_PERIOD) 100
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set ::env(RESET_PORT) "wb_rstn_i"
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## MASTER CLOCKS
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create_clock [get_ports {"wb_clk_i"} ] -name "wb_clk_i" -period $::env(WB_CLK_PERIOD)
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create_clock [get_ports {"user_clock"} ] -name "user_clock" -period $::env(WB_CLK_PERIOD)
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create_clock [get_ports {"mgmt_gpio_in[4]"} ] -name "mgmt_gpio_in" -period $::env(SCK_CLK_PERIOD)
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## GENERATED CLOCKS
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# NOTE: change the clock pins whenever the synthesis receipe changes
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create_generated_clock -name "wbbd_sck" -source [get_ports {"wb_clk_i"} ] -divide_by 1 [get_pins {"_9640_/Q"} ]
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create_generated_clock -name "csclk_fast" -source [get_pins {"_9640_/Q"}] -divide_by 1 [get_pins {"_8847_/X"} ]
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create_generated_clock -name "csclk_slow" -source [get_ports {"mgmt_gpio_in[4]"} ] -divide_by 1 [get_pins {"_8847_/X"} ]
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# serial_clock (twice the wb_clk_i frequency)
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create_generated_clock -name "serial_clock_pre" -source [get_ports {"wb_clk_i"} ] -multiply_by 2 [get_pins {"_9239_/Q"} ]
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create_generated_clock -name "serial_bb_clock" -source [get_pins {"_8847_/X"} ] -multiply_by 2 [get_pins {"_9772_/Q"} ]
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create_generated_clock -name "serial_clock_wb" -source [get_pins {"_9239_/Q"} ] -multiply_by 2 [get_pins {"_8819_/X"} ]
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create_generated_clock -name "serial_clock_bb" -source [get_pins {"_9772_/Q"} ] -multiply_by 2 [get_pins {"_8819_/X"} ]
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# paths between wb_clk_i and mgmt_gpio_in shouldn't be timed
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set_clock_groups -logically_exclusive -group wb_clk_i -group mgmt_gpio_in
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# mux output is logically exclusive
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set_clock_groups -logically_exclusive -group csclk_fast -group csclk_slow
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set_clock_groups -logically_exclusive -group serial_clock_wb -group serial_clock_bb
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## FALSE PATHS
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set_false_path -from [get_ports $::env(RESET_PORT)]
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set_false_path -from [get_ports "porb"]
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## INPUT/OUTPUT DELAYS
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set input_delay_value [expr $::env(WB_CLK_PERIOD) * $::env(IO_PCT)]
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set output_delay_value [expr $::env(WB_CLK_PERIOD) * $::env(IO_PCT)]
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puts "\[INFO\]: Setting output delay to: $output_delay_value"
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puts "\[INFO\]: Setting input delay to: $input_delay_value"
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set sck_clk_indx [lsearch [all_inputs] [get_port "mgmt_gpio_in[4]"]]
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#set rst_indx [lsearch [all_inputs] [get_port resetn]]
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set all_inputs_wo_clk [lreplace [all_inputs] $sck_clk_indx $sck_clk_indx]
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#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
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set all_inputs_wo_clk_rst $all_inputs_wo_clk
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set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk
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## OUTPUT DELAYS
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# WISHBONE DELAY
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set wb_output_delay 5
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set_output_delay $wb_output_delay -clock [get_clocks $::env(CLOCK_PORT)] [get_ports wb_ack_o]
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set_output_delay $wb_output_delay -clock [get_clocks $::env(CLOCK_PORT)] [get_ports wb_dat_o[*]]
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# PLL DELAYS
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_ena]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_dco_ena]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_div[*]]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_sel[*]]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll90_sel[*]]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_trim[*]]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_bypass[*]]
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# SOC DELAYS
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports ser_tx]
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# SPI DELAYS
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spi_sdi]
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# IRQ
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports irq[*]]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports reset]
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# GPIO
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# Specify serial_clock as a generated clock signal
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#set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_clock]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_load]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_resetn]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_data_1]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_data_2]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports mgmt_gpio_out[*]]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports mgmt_gpio_oeb[*]]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pwr_ctrl_out[*]]
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# FLASH
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spimemio_flash_io0_di]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spimemio_flash_io1_di]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spimemio_flash_io2_di]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spimemio_flash_io3_di]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports debug_in]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_csb]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_csb_oeb]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_clk]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_clk_oeb]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io0_oeb]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io1_oeb]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io0_ieb]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io1_ieb]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io0_do]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io1_do]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io0_ieb]
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# SRAM
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports sram_ro_clk]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports sram_ro_csb]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports sram_ro_addr[*]]
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# TODO set this as parameter
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set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
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set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
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puts "\[INFO\]: Setting load to: $cap_load"
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set_load $cap_load [all_outputs]
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## TIMING DERATE
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puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
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set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
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set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
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## CLOCK UNCERTAINITY
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puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {wb_clk_i}]
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {user_clock}]
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {mgmt_gpio_in}]
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## CLOCK TRANSITION
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puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {wb_clk_i}]
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {user_clock}]
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {mgmt_gpio_in}]
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## FANOUT
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set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design] |