mirror of https://github.com/efabless/caravel.git
147 lines
3.9 KiB
ReStructuredText
Executable File
147 lines
3.9 KiB
ReStructuredText
Executable File
.. raw:: html
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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SPI Controller
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==============
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This section describes the SPI configuration registers.
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Related pins
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------------
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- :ref:`SDI <sdi>` - E9,
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- :ref:`CSB <csb>` - E8,
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- :ref:`SCK <sck>` - F8,
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- :ref:`SDO <sdo>` - F9.
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.. _reg_spi_config:
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``reg_spi_config``
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------------------
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Base address: ``0x24000000``
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.. wavedrom::
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{ "reg": [
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{"name": "prescaler", "bits": 8},
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{"bits": 1, "name": "MLB"},
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{"bits": 1, "name": "nCSB"},
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{"bits": 1, "name": "nSCK"},
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{"bits": 1, "name": "MOD"},
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{"bits": 1, "name": "STM"},
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{"bits": 1, "name": "IE"},
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{"bits": 1, "name": "INT"},
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{"bits": 1, "name": "HK"},
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{"name": "(undefined, reads zero)", "type": 1, "bits": 16}],
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"config": {"hspace": 1400}
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}
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.. list-table:: Configuration bit definitions
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:name: spi_configuration_bit_definitions
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:header-rows: 1
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:widths: auto
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* - Bit
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- Name
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- Values
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* - 15
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- Housekeeping
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- 0 - SPI controller connected to external pins
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1 - SPI controller connected directly to housekeeping SPI
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* - 14
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- SPI interrupt enable
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- 0 - interrupt disabled
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1 - interrupt enabled ( :ref:`IRQ channel 9 <cpu_irq_channel_definitions>` )
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* - 13
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- SPI system enable
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- 0 - SPI disabled
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1 - SPI enabled
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* - 12
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- stream
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- 0 - apply/release :ref:`CSB <csb>` separately for each byte
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1 - apply :ref:`CSB <csb>` until stream bit is cleared (manually)
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* - 11
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- mode
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- 0 - read and change data on opposite :ref:`SCK <sck>` edges (default)
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1 - read and change data on the same :ref:`SCK <sck>` edges
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* - 10
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- invert :ref:`SCK <sck>`
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- 0 - normal :ref:`SCK <sck>` (default)
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1 - inverted :ref:`SCK <sck>`
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* - 9
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- invert :ref:`CSB <csb>`
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- 0 - normal :ref:`CSB <csb>` (low is active, default)
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1 - inverted :ref:`CSB <csb>` (high is active)
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* - 8
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- MLB
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- 0 - MSB first
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1 - LSB first
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* - 7-0
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- prescaler
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- count (in controller clock cycles) of 1/2 :ref:`SCK <sck>` cycle
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(default value 2). Clock rate formula:
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`SPI clock rate = 2 * core_clock / (prescaler + 1)`
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.. note::
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All configuration bits other than the prescaler default to value zero.
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.. _reg_spi_data:
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``reg_spi_data``
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----------------
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Base address: ``0x24000004``
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.. wavedrom::
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{ "reg": [
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{"name": "SPI data", "bits": 8},
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{"name": "(undefined, reads zero)", "type": 1, "bits": 24}]
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}
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The byte at ``0x24000004`` holds the SPI data (either read or write).
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Reading to and writing from the SPI controller is simply a matter of setting the required values in the configuration register, and writing values to or reading from ``reg_spi_data``.
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The protocol is similar to the UART.
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A write operation will stall the CPU if an incomplete SPI transmission is still in progress.
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Reading from the SPI will also stall the CPU if an incomplete SPI transmission is still in progress.
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There is no FIFO buffer for data.
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Therefore SPI reads and writes are relatively expensive operations that tie up the CPU, but will not lose or overwrite data.
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.. note::
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There is no FIFO associated with the SPI controller.
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