mirror of https://github.com/efabless/caravel.git
56 lines
2.1 KiB
Python
56 lines
2.1 KiB
Python
import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
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import cocotb.log
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from cpu import RiskV
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from defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP
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from caravel import GPIO_MODE
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bit_time_ns = 0
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reg = Regs()
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@cocotb.test()
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@repot_test
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async def spi_master_rd(dut):
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""" the firmware is configured to always send clk to spi so I can't insert alot of logics reading values
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the method of testing used can't work if 2 addresses Consecutive have the same address
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"""
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caravelEnv,clock = await test_configure(dut,timeout_cycles=214842)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info (f"[TEST] start spi_master_rd test")
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file_name = f"{os.getenv('CARAVEL_VERILOG_PATH')}/dv/cocotb/tests/spi_master/test_data"
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mem = read_mem(file_name)
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await cocotb.start(SPI_VIP(dut.bin33_monitor,dut.bin32_monitor,dut.bin35_monitor,(dut.bin34_en,dut.bin34),mem)) # fork for SPI
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addresses_to_read = (0x04,0x05,0x06,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf) # the addresses that the firmware read from mem file
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await wait_reg2(cpu,caravelEnv,0XAA)
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cocotb.log.info (f"[TEST] GPIO configuration finished ans start reading from mememory")
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val =0
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for address in addresses_to_read:
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# await wait_reg2(cpu,caravelEnv,0x55) # value is ready to be read
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#wait until value change
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while True:
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if val != cpu.read_debug_reg1():
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break
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await ClockCycles(caravelEnv.clk,100)
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expected_val = mem[address]
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val = cpu.read_debug_reg1()
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if val == expected_val:
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cocotb.log.info(f"[TEST] correct read of value {hex(val)} from address {hex(address)} ")
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else:
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cocotb.log.error(f"[TEST] wrong read from address {hex(address)} expected value = {hex(expected_val)} value {hex(val)} ")
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# cpu.write_debug_reg2_backdoor(0xCC)
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await ClockCycles(caravelEnv.clk,1000)
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