Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the ... signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).		2022-10-16 21:06:27 -04:00
..
dv	fix script to not create directory annotation_logs	2022-10-15 02:54:35 -07:00
gl	add mgmt_protect views and openlane files	2022-10-16 03:14:55 -07:00
rtl	Corrected the verilog and the layout for the caravan version of the	2022-10-16 21:06:27 -04:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00