mirror of https://github.com/efabless/caravel.git
149 lines
5.3 KiB
Verilog
149 lines
5.3 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*
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*-------------------------------------------------------------
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*
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* openframe_project_wrapper
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*
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* This wrapper enumerates all of the pins available to the
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* user for the user openframe project.
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*
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* Written by Tim Edwards
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* March 27, 2023
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* Efabless Corporation
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*
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*-------------------------------------------------------------
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*/
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module openframe_project_wrapper (
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`ifdef USE_POWER_PINS
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inout vdda, // User area 0 3.3V supply
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa, // User area 0 analog ground
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd, // Common 1.8V supply
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8v supply
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inout vssd, // Common digital ground
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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`endif
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/* Signals exported from the frame area to the user project */
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/* The user may elect to use any of these inputs. */
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input porb_h, // power-on reset, sense inverted, 3.3V domain
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input porb_l, // power-on reset, sense inverted, 1.8V domain
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input por_l, // power-on reset, noninverted, 1.8V domain
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input resetb_h, // master reset, sense inverted, 3.3V domain
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input resetb_l, // master reset, sense inverted, 1.8V domain
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input [31:0] mask_rev, // 32-bit user ID, 1.8V domain
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/* GPIOs. There are 44 GPIOs (19 left, 19 right, 6 bottom). */
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/* These must be configured appropriately by the user project. */
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/* Basic bidirectional I/O. Input gpio_in_h is in the 3.3V domain; all
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* others are in the 1.8v domain. OEB is output enable, sense inverted.
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*/
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input [`OPENFRAME_IO_PADS-1:0] gpio_in,
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input [`OPENFRAME_IO_PADS-1:0] gpio_in_h,
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output [`OPENFRAME_IO_PADS-1:0] gpio_out,
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output [`OPENFRAME_IO_PADS-1:0] gpio_oeb,
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/* Pad configuration. These signals are usually static values.
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* See the documentation for the sky130_fd_io__gpiov2 cell signals
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* and their use.
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*/
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output [`OPENFRAME_IO_PADS-1:0] gpio_inp_dis,
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output [`OPENFRAME_IO_PADS-1:0] gpio_ib_mode_sel,
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output [`OPENFRAME_IO_PADS-1:0] gpio_vtrip_sel,
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output [`OPENFRAME_IO_PADS-1:0] gpio_slow_sel,
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output [`OPENFRAME_IO_PADS-1:0] gpio_holdover,
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output [`OPENFRAME_IO_PADS-1:0] gpio_analog_en,
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output [`OPENFRAME_IO_PADS-1:0] gpio_analog_sel,
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output [`OPENFRAME_IO_PADS-1:0] gpio_analog_pol,
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output [`OPENFRAME_IO_PADS-1:0] gpio_dm2,
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output [`OPENFRAME_IO_PADS-1:0] gpio_dm1,
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output [`OPENFRAME_IO_PADS-1:0] gpio_dm0,
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/* These signals correct directly to the pad. Pads using analog I/O
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* connections should keep the digital input and output buffers turned
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* off. Both signals connect to the same pad. The "noesd" signal
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* is a direct connection to the pad; the other signal connects through
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* a series resistor which gives it minimal ESD protection. Both signals
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* have basic over- and under-voltage protection at the pad. These
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* signals may be expected to attenuate heavily above 50MHz.
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*/
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inout [`OPENFRAME_IO_PADS-1:0] analog_io,
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inout [`OPENFRAME_IO_PADS-1:0] analog_noesd_io,
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/* These signals are constant one and zero in the 1.8V domain, one for
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* each GPIO pad, and can be looped back to the control signals on the
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* same GPIO pad to set a static configuration at power-up.
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*/
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input [`OPENFRAME_IO_PADS-1:0] gpio_loopback_one,
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input [`OPENFRAME_IO_PADS-1:0] gpio_loopback_zero
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);
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`ifdef OPENFRAME_TESTING
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openframe_example test_example (
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`ifdef USE_POWER_PINS
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.vdda(vdda),
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.vdda1(vdda1),
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.vdda2(vdda2),
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.vssa(vssa),
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.vssa1(vssa1),
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.vssa2(vssa2),
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.vccd(vccd),
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.vccd1(vccd1),
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.vccd2(vccd2),
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.vssd(vssd),
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.vssd1(vssd1),
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.vssd2(vssd2),
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`endif
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.porb_h(porb_h),
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.porb_l(porb_l),
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.por_l(por_l),
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.resetb_h(resetb_h),
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.resetb_l(resetb_l),
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.mask_rev(mask_rev),
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.gpio_in(gpio_in),
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.gpio_in_h(gpio_in_h),
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.gpio_out(gpio_out),
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.gpio_oeb(gpio_oeb),
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.gpio_inp_dis(gpio_inp_dis),
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.gpio_ib_mode_sel(gpio_ib_mode_sel),
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.gpio_vtrip_sel(gpio_vtrip_sel),
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.gpio_slow_sel(gpio_slow_sel),
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.gpio_holdover(gpio_holdover),
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.gpio_analog_en(gpio_analog_en),
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.gpio_analog_sel(gpio_analog_sel),
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.gpio_analog_pol(gpio_analog_pol),
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.gpio_dm2(gpio_dm2),
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.gpio_dm1(gpio_dm1),
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.gpio_dm0(gpio_dm0),
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.analog_io(analog_io),
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.analog_noesd_io(analog_noesd_io),
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.gpio_loopback_one(gpio_loopback_one),
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.gpio_loopback_zero(gpio_loopback_zero)
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);
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`endif
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endmodule // openframe_project_wrapper
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