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caravel/verilog/dv/cocotb/tests/spi_master
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M0stafaRady ceac6defa1 fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
..
SPI_VIP.py Add hk_regs_wr_wb_cpu test 2022-10-04 03:24:15 -07:00
spi_master.py fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
spi_master_rd.c fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
spi_master_temp.c fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
test_data add new test spi_master_rd 2022-10-03 05:36:36 -07:00