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caravel/verilog
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Tim Edwards 2f74fa83ee Reinstated the logic analyzer as a standard interface for the 
management SoC.
 		2021-10-16 17:42:24 -04:00
..
dv/caravel First major update; current code passes syntax checks in iverilog 2021-10-15 21:49:49 -04:00
rtl Reinstated the logic analyzer as a standard interface for the 2021-10-16 17:42:24 -04:00