mirror of https://github.com/efabless/caravel.git
66 lines
3.5 KiB
Tcl
66 lines
3.5 KiB
Tcl
###############################################################################
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# Created by write_sdc
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# Fri Oct 14 12:15:45 2022
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###############################################################################
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current_design caravel_clocking
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name ext_clk -period 25.0000 [get_ports {ext_clk}]
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set_clock_transition 0.1500 [get_clocks {ext_clk}]
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set_clock_uncertainty 0.2000 ext_clk
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set_propagated_clock [get_clocks {ext_clk}]
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create_clock -name pll_clk -period 6.6667 [get_ports {pll_clk}]
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set_clock_transition 0.1000 [get_clocks {pll_clk}]
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set_clock_uncertainty 0.2000 pll_clk
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set_propagated_clock [get_clocks {pll_clk}]
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create_clock -name pll_clk90 -period 6.6667 [get_ports {pll_clk90}]
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set_clock_transition 0.1000 [get_clocks {pll_clk90}]
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set_clock_uncertainty 0.2000 pll_clk90
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set_propagated_clock [get_clocks {pll_clk90}]
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create_generated_clock -name core_clk -source [get_pins {_210_/X}] -divide_by 1 [get_ports {core_clk}]
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set_clock_transition 0.1000 [get_clocks {core_clk}]
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set_clock_uncertainty 0.2000 core_clk
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set_propagated_clock [get_clocks {core_clk}]
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set_clock_groups -name group1 -logically_exclusive \
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-group [get_clocks {ext_clk}]\
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-group [list [get_clocks {pll_clk}]\
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[get_clocks {pll_clk90}]]
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set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {ext_clk_sel}]
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set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[0]}]
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set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[1]}]
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set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[2]}]
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set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[0]}]
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set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[1]}]
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set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[2]}]
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set_output_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb_sync}]
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###############################################################################
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# Environment
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###############################################################################
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set_load -pin_load 0.2000 [get_ports {core_clk}]
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set_load -pin_load 0.2000 [get_ports {resetb_sync}]
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set_load -pin_load 0.2000 [get_ports {user_clk}]
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set_input_transition 5.0000 [get_ports {ext_clk}]
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set_input_transition 5.0000 [get_ports {ext_clk_sel}]
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set_input_transition 5.0000 [get_ports {ext_reset}]
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set_input_transition 5.0000 [get_ports {pll_clk}]
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set_input_transition 5.0000 [get_ports {pll_clk90}]
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set_input_transition 5.0000 [get_ports {resetb}]
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set_input_transition 5.0000 [get_ports {sel[2]}]
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set_input_transition 5.0000 [get_ports {sel[1]}]
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set_input_transition 5.0000 [get_ports {sel[0]}]
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set_input_transition 5.0000 [get_ports {sel2[2]}]
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set_input_transition 5.0000 [get_ports {sel2[1]}]
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set_input_transition 5.0000 [get_ports {sel2[0]}]
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set_timing_derate -early 0.9500
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set_timing_derate -late 1.0500
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###############################################################################
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# Design Rules
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###############################################################################
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set_max_transition 0.7500 [current_design]
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set_max_transition -clock_path 0.5000 [get_clocks {core_clk}]
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set_max_transition -clock_path 0.5000 [get_clocks {ext_clk}]
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set_max_transition -clock_path 0.5000 [get_clocks {pll_clk}]
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set_max_transition -clock_path 0.5000 [get_clocks {pll_clk90}]
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set_max_fanout 12.0000 [current_design]
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