mirror of https://github.com/efabless/caravel.git
46 lines
3.1 KiB
Plaintext
46 lines
3.1 KiB
Plaintext
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
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87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
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684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
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79cdb50a7dd60f69b63c0b6440b0dea35386387d verilog/rtl/__user_project_gpio_example.v
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5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v
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cc82a78753f5f5d0a1519bd81adbcff8a4296d91 verilog/rtl/__user_project_wrapper.v
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3c8c04f53b2848dc46132cda82c614e06e56571b verilog/rtl/buff_flash_clkrst.v
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2cc670e819a1cae69314242364118f5d4267737c verilog/rtl/caravan.v
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06e92151b5928e3f28e30a5cde76f7dd6530ed91 verilog/rtl/caravan_netlists.v
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a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
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5bc67d2d75579d06ab0d0395e634a08f39e3474b verilog/rtl/caravel.v
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2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
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625c9f974f1a3c9bd2eca5449a89a7bfb8f69fe8 verilog/rtl/caravel_logo.v
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1bbaa93405d4cb51429eacea4da40014231b11ed verilog/rtl/caravel_motto.v
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3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
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d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
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bc1e961e41d1d3a383a018279a08bf4108911f53 verilog/rtl/chip_io.v
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97c958944dd74a87f75d9fe2309837e567468722 verilog/rtl/chip_io_alt.v
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126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
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941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
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58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v
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653b230c7cbf092a6210ba7820bc942f312e53f3 verilog/rtl/debug_regs.v
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3d64219536ccda4c35a787682f13f45bc0ee8e94 verilog/rtl/digital_pll.v
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ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
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00d2c61e4f424dfce3635f96a1c1bfdeaf7d0cf8 verilog/rtl/gpio_control_block.v
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9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
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32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
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095aba3128be2f6f776ddf66596249c85471cd75 verilog/rtl/gpio_signal_buffering.v
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1a7e1e050b963054f5b62784249f713c90eaaaf0 verilog/rtl/gpio_signal_buffering_alt.v
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4290fcaf6bbcff701c2c47c7a23ce4fd4698e888 verilog/rtl/housekeeping.v
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3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
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ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
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3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
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9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
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c96ba94e5779ea6afe452d89632eaada73e26aab verilog/rtl/mprj_io.v
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3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
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5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v
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4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v
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669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
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6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v
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1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v
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8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
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c94f7ed5aa311f005513ace344991c8e6d3d19f5 scripts/set_user_id.py
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98168b1fb6f80b196f9a05e725ec6ad99bc57ac6 scripts/generate_fill.py
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3210e724c6dc99563af780ff1778fada5b432604 scripts/compositor.py
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