mirror of https://github.com/efabless/caravel.git
155 lines
4.3 KiB
Tcl
155 lines
4.3 KiB
Tcl
# Power nets
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if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
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if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
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foreach power_pin $::env(STD_CELL_POWER_PINS) {
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add_global_connection \
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-net $::env(VDD_NET) \
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-inst_pattern .* \
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-pin_pattern $power_pin \
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-power
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}
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foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
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add_global_connection \
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-net $::env(GND_NET) \
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-inst_pattern .* \
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-pin_pattern $ground_pin \
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-ground
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}
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}
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}
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if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 &&
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[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
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set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
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foreach pdn_hook $pdn_hooks {
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set instance_name [lindex $pdn_hook 0]
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set power_net [lindex $pdn_hook 1]
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set ground_net [lindex $pdn_hook 2]
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set power_pin [lindex $pdn_hook 3]
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set ground_pin [lindex $pdn_hook 4]
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if { $power_pin == "" || $ground_pin == "" } {
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puts "FP_PDN_MACRO_HOOKS missing power and ground pin names"
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exit -1
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}
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add_global_connection \
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-net $power_net \
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-inst_pattern $instance_name \
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-pin_pattern $power_pin \
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-power
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add_global_connection \
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-net $ground_net \
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-inst_pattern $instance_name \
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-pin_pattern $ground_pin \
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-ground
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}
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}
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set secondary []
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foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
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if { $vdd != $::env(VDD_NET)} {
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lappend secondary $vdd
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set db_net [[ord::get_db_block] findNet $vdd]
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if {$db_net == "NULL"} {
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set net [odb::dbNet_create [ord::get_db_block] $vdd]
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$net setSpecial
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$net setSigType "POWER"
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}
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}
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if { $gnd != $::env(GND_NET)} {
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lappend secondary $gnd
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set db_net [[ord::get_db_block] findNet $gnd]
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if {$db_net == "NULL"} {
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set net [odb::dbNet_create [ord::get_db_block] $gnd]
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$net setSpecial
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$net setSigType "GROUND"
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}
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}
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}
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puts "set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
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-secondary_power $secondary"
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set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
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-secondary_power $secondary
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# Assesses whether the design is the core of the chip or not based on the
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# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
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define_pdn_grid \
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-name stdcell_grid \
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-starts_with POWER \
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-voltage_domain CORE \
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-pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(FP_PDN_LOWER_LAYER) \
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-width $::env(FP_PDN_VWIDTH) \
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-pitch 25 \
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-offset 9.0 \
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-spacing 10.9 \
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-nets "vccd vssd" \
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-starts_with POWER -extend_to_core_ring
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(FP_PDN_LOWER_LAYER) \
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-width $::env(FP_PDN_VWIDTH) \
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-pitch 25 \
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-offset 14.0 \
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-spacing 10.9 \
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-nets "vccd1 vssd1" \
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-starts_with POWER -extend_to_core_ring
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(FP_PDN_UPPER_LAYER) \
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-width $::env(FP_PDN_HWIDTH) \
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-pitch 16.9 \
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-offset 9.22 \
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-spacing 6.85 \
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-nets "vccd1 vssd1"\
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-starts_with POWER -extend_to_core_ring
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(FP_PDN_UPPER_LAYER) \
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-width $::env(FP_PDN_HWIDTH) \
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-pitch 16.9 \
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-offset 3.98 \
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-spacing 6.85 \
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-nets "vccd vssd"\
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-starts_with POWER -extend_to_core_ring
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add_pdn_connect \
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-grid stdcell_grid \
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-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(FP_PDN_RAILS_LAYER) \
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-width $::env(FP_PDN_RAIL_WIDTH) \
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-followpins \
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-starts_with POWER
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add_pdn_connect \
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-grid stdcell_grid \
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-layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
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define_pdn_grid \
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-macro \
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-default \
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-name macro \
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-starts_with POWER \
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-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
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add_pdn_connect \
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-grid macro \
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-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
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