mirror of https://github.com/efabless/caravel.git
204 lines
9.3 KiB
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204 lines
9.3 KiB
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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===========================
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Caravel digital locked loop
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===========================
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The Caravel digital locked loop ``DLL`` is an all-digital clock generating
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module.
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The GPIO pins on Caravel have a limit of 50MHz input. Internally, it is
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possible to generate a clean oscillation of up to around 200MHz or higher.
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To ensure large margins of safety, the Caravel demonstration board ships
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with an on-board oscillator of 10MHz. The operational frequency of the
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management SoC on Caravel differs according to which management SoC
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architecture is present, but is generally in the range of around 50MHz.
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The DLL comprises an on-chip tunable ring oscillator and a feedback
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controller for locking to a known input clock. It can operate in either
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free-running ``DCO`` or locked ``DLL`` modes. The Caravel system can run
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directly off of the external clock (bypass mode), the free-running DCO,
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or the DLL locked to the external clock.
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The DLL's tunable oscillator has an operating range of approximately
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75MHz to 150MHz. The oscillator is a loop of from 13 to 39 inverter
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stages with 26 bits of trim. Each trim bit adds or subtracts one of
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the stages. So there are 27 effective frequency steps covering a range
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of about 75MHz, with an incremental delay of about 250ps per step.
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In the Caravel memory map, the DLL is controlled by a handful of registers
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as shown below. These registers are in the housekeeping SPI module, and
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so can be controlled either from an external source through the housekeeping
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SPI, or internally through the management SoC.
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**WARNING:**
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The management SoC altering its own clock has not yet been tested
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as of this writing; however, the core clock should be guaranteed to be glitch-
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free through transistions from external clock to DLL output and vice versa.
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-------------
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DLL operation
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-------------
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The DLL operates by taking the ring oscillator output, reducing its frequency
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through a feedback divider, and comparing the result to the input clock.
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If the frequency of the divided-down ring oscillator output is faster than
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the input clock frequency, then an additional delay stage is added to the
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ring oscillator, making it run slower. If the frequency of the divided-down
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ring oscillator output is slower than the input clock frequency, then a delay
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stage is subtracted from the ring oscillator, making it faster. This
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operation is performed in a continuous loop to keep the DLL frequency locked
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to the input clock.
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**WARNING:**
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Using discrete delay state insertion and removal results in high
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phase noise (cycle to cycle jitter) on the core clock when running in DLL mode,
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due to instantaneous changes of 250ps between cycles (a 0.25% change in the
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clock period). User projects that require a clock with low phase noise should
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use the external clock (DLL in bypass mode), and if the project requires a
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higher clock rate, then the 10MHz clock on the demonstration board may be
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replaced with another oscillator of the same footprint with a frequency up
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to 50MHz. The DLL running in DCO mode has low cycle-to-cycle jitter but will
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have a large drift component, as it is not temperature stabilized.
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The DLL controls are memory-mapped to the housekeeping space, and are as follows:
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=================================================================================
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- Register name = ``reg_hkspi_pll_ena``
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- Memory location = ``0x2610000c``
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- Housekeeping SPI location = ``0x08``
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| 0x09 | | | | | | | DCO | DLL |
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| | | | | | | | ena | ena |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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bit 1: DCO enable
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value 0 = DCO disabled. DLL runs in active locking mode
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value 1 = DCO enabled. DLL runs in DCO mode.
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bit 0: DLL enable
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value 0 = DLL disabled. DLL is disabled and the clock is stopped.
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value 1 = DLL enabled. DLL is enabled and outputs a clock.
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=============================================================================
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- Register name = ``reg_hkspi_pll_bypass``
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- Memory location = ``0x26100010``
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- Housekeeping SPI location = ``0x09``
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| 0x09 | | | | | | | | DLL |
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| | | | | | | | | bypass|
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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bit 0: DLL bypass
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value 0 = DLL active. Core clock is derived from the DLL output.
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value 1 = DLL bypassed. Core clock is derived from the external clock source.
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=============================================================================
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- Register name = ``reg_hkspi_pll_trim``
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- Memory location = ``0x2610001c to 0x261001f``
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- Housekeeping SPI location = ``0x0d to 0x10``
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| 0x10 | | | | | | | trim25| trim24|
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| 0x0f | trim23| trim22| trim21| trim20| trim19| trim18| trim17| trim16|
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| 0x0e | trim15| trim14| trim13| trim12| trim11| trim10| trim9 | trim8 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| 0x0d | trim7 | trim6 | trim5 | trim4 | trim3 | trim2 | trim1 | trim0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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**All bits:**
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DLL manual trim value. This 26-bit value is applied to
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the DLL when in DCO mode and directly controls the frequency
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of the ring oscillator. Each '1' bit turns on one delay
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stage in the oscillator.
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**NOTE:**
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The phase relationship between the DLL outputs (for the core
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clock and the user clock) is nominally 90 degrees when the trim
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stages are balanced along the length of the oscillator, but this
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phase can be altered with non-uniform delays.
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=============================================================================
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- Register name = ``reg_hkspi_pll_divider``
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- Memory location = ``0x26100024``
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- Housekeeping SPI location = ``0x12``
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| 0x12 | | | | div4 | div3 | div2 | div1 | div0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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bits 4 to 0: Value of the DLL feedback divider. In active DLL mode,
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the DLL output is divided down by this amount, and then the
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trim is adjusted to make the divided value match the incoming
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external clock.
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For example, if the external clock is 10MHz and the divider value is
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9 (div = 5'b01001), then the DLL will trim the oscillator to run at
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10MHz * 9 = 90MHz. The value of (external clock frequency * divider
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value) must always be within the DLL's trimmable range, or else the
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DLL will saturate.
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=============================================================================
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- Register name = ``reg_hkspi_pll_source``
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- Memory location = ``0x26100020``
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- Housekeeping SPI location = ``0x11``
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| 0x11 | | | core2 | core1 | core0 | user2 | user1 | user0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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bits 2 to 0: Value of the user clock output divider. The value of
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the secondary clock ("user_clock") in the user project area
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is derived from the zero-phase ring oscillator output divided
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down by this amount. The values range from 1 (divide by 1)
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to 7 (divide by 7).
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bits 5 to 3: Value of the core clock output divider. The value of
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the primary clock ("wb_clk_i") in the user project area
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is derived from the 90-degree-phase ring oscillator output
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divided down by this amount. The values range from 1 (divide
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by 1) to 7 (divide by 7).
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