caravel/verilog
Tim Edwards 298ede362b Corrects an issue with the user pass-through flash programming
mode in which the data and clock are activated simultaneously,
so the first data bit after CSB goes low may or may not be
seen by the SPI flash.
2022-06-07 10:42:56 -04:00
..
dv Introduction of PDK variable (#39) 2022-04-08 09:05:58 -07:00
gl fixed caravel netlist to use the 1803 defaults block (#94) 2022-05-03 10:36:11 -07:00
rtl Corrects an issue with the user pass-through flash programming 2022-06-07 10:42:56 -04:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00