mirror of https://github.com/efabless/caravel.git
88 lines
2.6 KiB
Tcl
88 lines
2.6 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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package require openlane
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set script_dir [file dirname [file normalize [info script]]]
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set save_path $script_dir/../..
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prep -design $script_dir -tag gpio_control_block -overwrite
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run_synthesis
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init_floorplan
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set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/gpio_control_block.io.def]
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try_catch openroad -exit $script_dir/io_place.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(floorplan_logs)/io.log 0]
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set_def $::env(SAVE_DEF)
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file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/placement/macro_placement.cfg
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manual_macro_placement f
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tap_decap_or
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run_power_grid_generation
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run_placement
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run_cts
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run_resizer_timing
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run_routing
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if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
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run_antenna_check
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heal_antenna_violators; # modifies the routed DEF
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}
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run_magic
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run_magic_spice_export
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set powered_netlist_name [index_file $::env(finishing_tmpfiles)/powered_netlist.v]
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set powered_def_name [index_file $::env(finishing_tmpfiles)/powered_def.def]
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write_powered_verilog\
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-output_verilog $powered_netlist_name\
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-output_def $powered_def_name\
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-log $::env(finishing_logs)/write_verilog.log\
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-def_log $::env(finishing_logs)/write_powered_def.log
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set_netlist $powered_netlist_name
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run_magic_drc
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run_lvs
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run_antenna_check
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run_lef_cvc
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save_views -save_path $save_path \
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-def_path $::env(CURRENT_DEF) \
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-lef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef \
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-gds_path $::env(finishing_results)/$::env(DESIGN_NAME).gds \
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-mag_path $::env(finishing_results)/$::env(DESIGN_NAME).mag \
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-maglef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef.mag \
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-spice_path $::env(finishing_results)/$::env(DESIGN_NAME).spice \
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-verilog_path $::env(CURRENT_NETLIST) \
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-spef_path $::env(SPEF_TYPICAL) \
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-sdf_path $::env(CURRENT_SDF) \
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-sdc_path $::env(CURRENT_SDC)
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calc_total_runtime
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save_state
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generate_final_summary_report
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check_timing_violations
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