mirror of https://github.com/efabless/caravel.git
80 lines
1.8 KiB
Verilog
80 lines
1.8 KiB
Verilog
module constant_block (one,
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zero,
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vccd,
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vssd);
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output one;
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output zero;
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input vccd;
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input vssd;
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wire one_unbuf;
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wire zero_unbuf;
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sky130_fd_sc_hd__buf_16 const_one_buf (.A(one_unbuf),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd),
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.X(one));
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sky130_fd_sc_hd__conb_1 const_source (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd),
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.HI(one_unbuf),
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.LO(zero_unbuf));
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sky130_fd_sc_hd__buf_16 const_zero_buf (.A(zero_unbuf),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd),
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.X(zero));
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sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_0 (.VGND(vssd),
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.VPWR(vccd));
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sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1 (.VGND(vssd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_2 FILLER_0_0 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_2 FILLER_0_24 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_1 FILLER_0_27 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_4 FILLER_1_0 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_1 FILLER_1_4 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_8 FILLER_1_8 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_8 FILLER_1_16 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_4 FILLER_1_24 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_2 FILLER_2_0 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_2 FILLER_2_24 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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endmodule
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