mirror of https://github.com/efabless/caravel.git
104 lines
7.2 KiB
Tcl
104 lines
7.2 KiB
Tcl
###############################################################################
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# Created by write_sdc
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# Wed Nov 24 18:33:22 2021
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###############################################################################
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current_design spare_logic_block
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name __VIRTUAL_CLK__ -period 10.0000
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set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xfq[0]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xfq[1]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xfqn[0]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xfqn[1]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xi[0]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xi[1]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xi[2]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xi[3]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xib}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xmx[0]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xmx[1]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xna[0]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xna[1]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xno[0]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xno[1]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[0]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[10]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[11]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[12]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[13]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[14]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[15]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[16]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[17]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[18]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[19]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[1]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[20]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[21]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[22]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[23]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[24]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[25]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[26]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[2]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[3]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[4]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[5]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[6]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[7]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[8]}]
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set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[9]}]
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###############################################################################
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# Environment
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###############################################################################
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set_load -pin_load 0.0334 [get_ports {spare_xib}]
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set_load -pin_load 0.0334 [get_ports {spare_xfq[1]}]
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set_load -pin_load 0.0334 [get_ports {spare_xfq[0]}]
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set_load -pin_load 0.0334 [get_ports {spare_xfqn[1]}]
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set_load -pin_load 0.0334 [get_ports {spare_xfqn[0]}]
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set_load -pin_load 0.0334 [get_ports {spare_xi[3]}]
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set_load -pin_load 0.0334 [get_ports {spare_xi[2]}]
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set_load -pin_load 0.0334 [get_ports {spare_xi[1]}]
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set_load -pin_load 0.0334 [get_ports {spare_xi[0]}]
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set_load -pin_load 0.0334 [get_ports {spare_xmx[1]}]
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set_load -pin_load 0.0334 [get_ports {spare_xmx[0]}]
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set_load -pin_load 0.0334 [get_ports {spare_xna[1]}]
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set_load -pin_load 0.0334 [get_ports {spare_xna[0]}]
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set_load -pin_load 0.0334 [get_ports {spare_xno[1]}]
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set_load -pin_load 0.0334 [get_ports {spare_xno[0]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[26]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[25]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[24]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[23]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[22]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[21]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[20]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[19]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[18]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[17]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[16]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[15]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[14]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[13]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[12]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[11]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[10]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[9]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[8]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[7]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[6]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[5]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[4]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[3]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[2]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[1]}]
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set_load -pin_load 0.0334 [get_ports {spare_xz[0]}]
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set_timing_derate -early 0.9500
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set_timing_derate -late 1.0500
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###############################################################################
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# Design Rules
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###############################################################################
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set_max_fanout 5.0000 [current_design]
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