caravel/signoff/caravel_clocking/openlane.log

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[INFO]: Run Directory: /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/caravel_clocking/runs/23_03_06_03_51
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[INFO]: Running Synthesis (log: caravel_clocking/runs/23_03_06_03_51/logs/synthesis/1-synthesis.log)...
[INFO]: Running Single-Corner Static Timing Analysis (log: caravel_clocking/runs/23_03_06_03_51/logs/synthesis/2-sta.log)...
[INFO]: Running Initial Floorplanning (log: caravel_clocking/runs/23_03_06_03_51/logs/floorplan/3-initial_fp.log)...
[INFO]: Floorplanned with width 93.38 and height 89.76.
[INFO]: Running IO Placement (log: caravel_clocking/runs/23_03_06_03_51/logs/floorplan/4-place_io.log)...
[INFO]: Running Tap/Decap Insertion (log: caravel_clocking/runs/23_03_06_03_51/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {VPWR} and ground {VGND}...
[INFO]: Generating PDN (log: caravel_clocking/runs/23_03_06_03_51/logs/floorplan/6-pdn.log)...
[INFO]: Running Global Placement (log: caravel_clocking/runs/23_03_06_03_51/logs/placement/7-global.log)...
[INFO]: Running Placement Resizer Design Optimizations (log: caravel_clocking/runs/23_03_06_03_51/logs/placement/8-resizer.log)...
[INFO]: Running Detailed Placement (log: caravel_clocking/runs/23_03_06_03_51/logs/placement/9-detailed.log)...
[INFO]: Running Clock Tree Synthesis (log: caravel_clocking/runs/23_03_06_03_51/logs/cts/10-cts.log)...
[INFO]: Running Placement Resizer Timing Optimizations (log: caravel_clocking/runs/23_03_06_03_51/logs/cts/11-resizer.log)...
[INFO]: Removing Buffers from Nets (If Applicable) (log: caravel_clocking/runs/23_03_06_03_51/logs/placement/12-remove_buffers.log)...
[INFO]: Running custom buffer script
[INFO]: Running Global Routing Resizer Timing Optimizations (log: caravel_clocking/runs/23_03_06_03_51/logs/routing/13-resizer.log)...
[INFO]: Running Diode Insertion (log: caravel_clocking/runs/23_03_06_03_51/logs/routing/14-diodes.log)...
[INFO]: Running Detailed Placement (log: caravel_clocking/runs/23_03_06_03_51/logs/routing/15-diode_legalization.log)...
[INFO]: Running Fill Insertion (log: caravel_clocking/runs/23_03_06_03_51/logs/routing/16-fill.log)...
[INFO]: Running Global Routing (log: caravel_clocking/runs/23_03_06_03_51/logs/routing/17-global.log)...
[INFO]: Writing Verilog (log: caravel_clocking/runs/23_03_06_03_51/logs/routing/17-global_write_netlist.log)...
[INFO]: Running Detailed Routing (log: caravel_clocking/runs/23_03_06_03_51/logs/routing/19-detailed.log)...
[INFO]: No DRC violations after detailed routing.
[INFO]: Running SPEF Extraction at the min process corner (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/20-parasitics_extraction.min.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the min process corner (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/21-rcx_mcsta.min.log)...
[INFO]: Running SPEF Extraction at the max process corner (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/22-parasitics_extraction.max.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the max process corner (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/23-rcx_mcsta.max.log)...
[INFO]: Running SPEF Extraction at the nom process corner (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/24-parasitics_extraction.nom.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/25-rcx_mcsta.nom.log)...
[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/26-rcx_sta.log)...
[INFO]: Creating IR Drop Report (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/27-irdrop.log)...
[INFO]: Running Magic to generate various views...
[INFO]: Streaming out GDSII with Magic (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/28-gdsii.log)...
[INFO]: Generating MAGLEF views...
[INFO]: Running Magic Spice Export from LEF (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/29-spice.log)...
[INFO]: Writing Powered Verilog (logs: caravel_clocking/runs/23_03_06_03_51/logs/signoff/30-write_powered_def.log, caravel_clocking/runs/23_03_06_03_51/logs/signoff/30-write_powered_verilog.log)...
[INFO]: Writing Verilog (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/30-write_powered_verilog.log)...
[INFO]: Running LVS (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/32-lvs.lef.log)...
[INFO]: Running Magic DRC (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/33-drc.log)...
[INFO]: Converting Magic DRC database to various tool-readable formats...
[INFO]: No DRC violations after GDS streaming out.
[INFO]: Running OpenROAD Antenna Rule Checker (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/34-antenna.log)...
[WARNING]: The command run_lef_cvc is now deprecated; use run_erc instead.
[INFO]: Running Circuit Validity Checker ERC (log: caravel_clocking/runs/23_03_06_03_51/logs/signoff/35-erc_screen.log)...
[INFO]: Saving current set of views in 'caravel_clocking/runs/23_03_06_03_51/results/final'...
[INFO]: Saving current set of views in '..'...
[INFO]: Saving runtime environment...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'caravel_clocking/runs/23_03_06_03_51/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'caravel_clocking/runs/23_03_06_03_51/reports/metrics.csv'.
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to 'caravel_clocking/runs/23_03_06_03_51/reports/signoff/26-rcx_sta.slew.rpt'.
[INFO]: There are no hold violations in the design at the typical corner.
[INFO]: There are no setup violations in the design at the typical corner.