mirror of https://github.com/efabless/caravel.git
153 lines
4.5 KiB
Tcl
153 lines
4.5 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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package require openlane
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set script_dir [file dirname [file normalize [info script]]]
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set save_path $script_dir/../..
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# FOR LVS AND CREATING PORT LABELS
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set ::env(USE_GPIO_ROUTING_LEF) 0
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prep -design $script_dir -tag chip_io_alt_lvs -overwrite
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# Needed for the sky130_ef_io__analog_pad verilog views
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set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
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verilog_elaborate
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#init_floorplan
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#file copy -force $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
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#file copy -force $::env(CURRENT_NETLIST) $::env(TMP_DIR)/lvs.v
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# ACTUAL CHIP INTEGRATION
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set ::env(USE_GPIO_ROUTING_LEF) 1
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prep -design $script_dir -tag chip_io_alt -overwrite
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# file copy $script_dir/runs/chip_io_alt_lvs/tmp/merged_unpadded.lef $::env(TMP_DIR)/lvs.lef
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# file copy $script_dir/runs/chip_io_alt_lvs/tmp/lvs.def $::env(TMP_DIR)/lvs.def
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# file copy $script_dir/runs/chip_io_alt_lvs/tmp/lvs.v $::env(TMP_DIR)/lvs.v
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set ::env(SYNTH_DEFINES) "TOP_ROUTING USE_POWER_PINS"
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verilog_elaborate
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#init_floorplan
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puts_info "Generating pad frame"
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exec python3 $::env(SCRIPTS_DIR)/padringer.py\
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--def-netlist $::env(CURRENT_DEF)\
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--design $::env(DESIGN_NAME)\
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--lefs $::env(TECH_LEF) {*}$::env(GPIO_PADS_LEF)\
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-cfg $script_dir/padframe.cfg\
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--working-dir $::env(TMP_DIR)\
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-o $::env(RESULTS_DIR)/floorplan/padframe.def 2>&1
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puts_info "Generated pad frame"
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set_def $::env(RESULTS_DIR)/floorplan/padframe.def
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# modify to a different file
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remove_pins -input $::env(CURRENT_DEF)
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remove_empty_nets -input $::env(CURRENT_DEF)
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set core_obs "
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met1 225 235 3365 4950, \
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met2 225 235 3365 4950, \
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met3 225 235 3365 4950, \
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met4 225 235 3365 4955, \
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met5 225 235 3365 4955
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"
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set gpio_m3_pins_west_0 "met3 198.400 1002.125 215.185 2202.125"
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set gpio_m3_pins_west_1 "met3 198.400 2726.820 215.185 4126.82"
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set gpio_m3_pins_west_2 "met3 198.400 4641.655 215.185 4755.305"
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set gpio_m3_pins_east "met3 3370.840 600.050 3387.01 4731.99"
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# South Power Pads
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set vssa_south_obs "
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met3 393.99000 198.45500 468.60000 222.76000"
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set vssd_south_obs "
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met3 1205.66500 196.21000 1280.500 276.98500"
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set vssio_south_obs "
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met3 2845.04000 198.49500 2919.58500 230.61000"
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# East Power Pads
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set vssa1_p2_east_obs "
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met3 3317.33500 2040.81500 3389.89500 2117.49500"
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set vssd1_east_obs "
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met3 3316.26500 2285.19500 3379.17500 2385.12500, \
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met4 3316.26500 2285.19500 3379.17500 2385.12500"
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set vdda1_p2_east_obs "
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met3 3338.51500 2474.03500 3389.27500 2550.56000, \
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met4 3338.51500 2474.03500 3389.27500 2550.5600"
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set vdda1_east_obs "
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met3 3340.13500 4017.53500 3385.45000 4094.53500"
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set ::env(GLB_RT_OBS) "
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$core_obs, \
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$gpio_m3_pins_west_0, \
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$gpio_m3_pins_west_1, \
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$gpio_m3_pins_west_2, \
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$gpio_m3_pins_east, \
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$vssd_south_obs, \
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$vssio_south_obs, \
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$vssd1_east_obs, \
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$vdda1_p2_east_obs, \
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$vdda1_east_obs
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"
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try_catch python3 $::env(SCRIPTS_DIR)/add_def_obstructions.py \
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--input-def $::env(CURRENT_DEF) \
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--lef $::env(MERGED_LEF) \
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--obstructions $::env(GLB_RT_OBS) \
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--output [file rootname $::env(CURRENT_DEF)].obs.def |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/obs.log
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set_def [file rootname $::env(CURRENT_DEF)].obs.def
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li1_hack_start
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global_routing
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detailed_routing
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li1_hack_end
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label_macro_pins\
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-lef $::env(TMP_DIR)/lvs.lef\
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-netlist_def $::env(TMP_DIR)/lvs.def\
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-pad_pin_name "PAD"
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run_magic
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# run_magic_drc
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run_magic_spice_export
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save_views -lef_path $::env(magic_result_file_tag).lef \
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-def_path $::env(CURRENT_DEF) \
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-gds_path $::env(magic_result_file_tag).gds \
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-mag_path $::env(magic_result_file_tag).mag \
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-maglef_path $::env(magic_result_file_tag).lef.mag \
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-verilog_path $::env(TMP_DIR)/lvs.v \
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-spice_path $::env(magic_result_file_tag).spice \
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-save_path $save_path \
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-tag $::env(RUN_TAG)
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run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v
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calc_total_runtime
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generate_final_summary_report |