mirror of https://github.com/efabless/caravel.git
78 lines
2.1 KiB
Verilog
78 lines
2.1 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*
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*---------------------------------------------------------------------
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* A simple module that generates buffered high and low outputs
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* in the 1.8V domain.
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*---------------------------------------------------------------------
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*/
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module constant_block (
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`ifdef USE_POWER_PINS
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inout vccd,
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inout vssd,
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`endif
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output one,
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output zero
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);
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wire one_unbuf;
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wire zero_unbuf;
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sky130_fd_sc_hd__conb_1 const_source (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.HI(one_unbuf),
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.LO(zero_unbuf)
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);
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/* Buffer the constant outputs (could be synthesized) */
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/* NOTE: Constant cell HI, LO outputs are connected to power */
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/* rails through an approximately 120 ohm resistor, which is not */
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/* enough to drive inputs in the I/O cells while ensuring ESD */
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/* requirements, without buffering. */
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sky130_fd_sc_hd__buf_16 const_one_buf (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.A(one_unbuf),
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.X(one)
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);
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sky130_fd_sc_hd__buf_16 const_zero_buf (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.A(zero_unbuf),
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.X(zero)
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);
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endmodule
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`default_nettype wire
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