mirror of https://github.com/efabless/caravel.git
357 lines
17 KiB
Python
Executable File
357 lines
17 KiB
Python
Executable File
#!/usr/bin/python3
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# -*- coding: utf-8 -*-
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import collections
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import json
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import sys
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import os
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from pathlib import Path
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import json
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from fnmatch import fnmatch
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from datetime import datetime
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import random
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from pathlib import Path
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iverilog = True
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vcs = False
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coverage = False
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def go_up(path, n):
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for i in range(n):
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path = os.path.dirname(path)
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return path
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# search pattern in file
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def search_str(file_path, word):
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with open(file_path, 'r') as file:
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# read all content of a file
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content = file.read()
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# check if string present in a file
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if word in content:
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return "passed"
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else:
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return "failed"
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class RunTest:
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def __init__(self,test_name,sim) -> None:
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self.cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb"
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self.test_name = test_name
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self.sim_type = sim
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self.create_log_file()
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self.hex_generate()
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self.runTest()
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# create and open full terminal log to be able to use it before run the test
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def create_log_file(self):
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self.cd_cocotb()
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os.chdir(f"sim/{os.getenv('RUNTAG')}")
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test_dir = f"{self.sim_type}-{self.test_name}"
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os.makedirs(f"{test_dir}",exist_ok=True)
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self.cd_cocotb()
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self.sim_path = f"sim/{os.getenv('RUNTAG')}/{test_dir}/"
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terminal_log=f"{self.sim_path}/fullTerminal.log"
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test_log=f"{self.sim_path}/{self.test_name}.log"
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self.full_terminal = open(test_log, "w")
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def runTest(self):
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if (iverilog):return self.runTest_iverilog()
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elif(vcs): return self.runTest_vcs()
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# iverilog function
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def runTest_iverilog(self):
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CARAVEL_ROOT = os.getenv('CARAVEL_ROOT')
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CARAVEL_VERILOG_PATH = os.getenv('CARAVEL_VERILOG_PATH')
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MCW_ROOT = os.getenv('MCW_ROOT')
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VERILOG_PATH = os.getenv('VERILOG_PATH')
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CARAVEL_PATH = os.getenv('CARAVEL_PATH')
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USER_PROJECT_VERILOG = os.getenv('USER_PROJECT_VERILOG')
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FIRMWARE_PATH = os.getenv('FIRMWARE_PATH')
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RUNTAG = os.getenv('RUNTAG')
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ERRORMAX = os.getenv('ERRORMAX')
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PDK_ROOT = os.getenv('PDK_ROOT')
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PDK = os.getenv('PDK')
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env_vars = f"-e {CARAVEL_ROOT} -e CARAVEL_VERILOG_PATH={CARAVEL_VERILOG_PATH} -e MCW_ROOT={MCW_ROOT} -e VERILOG_PATH={VERILOG_PATH} -e CARAVEL_PATH={CARAVEL_PATH} -e USER_PROJECT_VERILOG={USER_PROJECT_VERILOG} -e FIRMWARE_PATH={FIRMWARE_PATH} -e RUNTAG={RUNTAG} -e ERRORMAX={ERRORMAX} -e PDK_ROOT={PDK_ROOT} -e PDK={PDK}"
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print(f"Start running test: {self.sim_type}-{self.test_name}")
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command = f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} "
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os.system(f"docker run -it {env_vars} -v {os.getenv('CARAVEL_ROOT')}:{os.getenv('CARAVEL_ROOT')} -v {os.getenv('MCW_ROOT')}:{os.getenv('MCW_ROOT')} -v {os.getenv('PDK_ROOT')}:{os.getenv('PDK_ROOT')} efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {command}'")
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self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
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Path(f'{self.sim_path}/{self.passed}').touch()
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# vcs function
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def runTest_vcs(self):
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print(f"Start running test: {self.sim_type}-{self.test_name}")
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PDK_ROOT = os.getenv('PDK_ROOT')
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PDK = os.getenv('PDK')
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VERILOG_PATH = os.getenv('VERILOG_PATH')
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dirs = f'+incdir+\\\"{PDK_ROOT}/{PDK}\\\" '
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if self.sim_type == "RTL":
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dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/rtl_caravel_vcs.list\\\" '
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else:
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dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/gl_caravel_vcs.list\\\" '
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macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS '
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if self.test_name == "la":
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macros = f'{macros} +define+LA_TESTING'
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if self.test_name in ["gpio_all_o_user","gpio_all_i_user","gpio_all_i_pu_user","gpio_all_i_pd_user","gpio_all_bidir_user"]:
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macros = f'{macros} +define+GPIO_TESTING'
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# shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex')
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# if os.path.exists(f'{self.test_full_dir}/test_data'):
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# shutil.copyfile(f'{self.test_full_dir}/test_data',f'{self.sim_path}/test_data')
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if (self.sim_type=="GL_SDF"):
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macros = f'{macros} +define+ENABLE_SDF +define+SIM=GL_SDF +define+GL +define+SDF_POSTFIX=\\\"-{self.corner}\\\"'
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os.makedirs(f"annotation_logs",exist_ok=True)
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elif(self.sim_type=="GL"):
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macros = f'{macros} +define+GL +define+SIM=GL'
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elif (self.sim_type=="RTL"):
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macros = f'{macros} +define+SIM=\\\"RTL\\\"'
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else:
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print(f"Fatal: incorrect simulation type {self.sim_type}")
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coverage_command = ""
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if coverage:
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coverage_command = "-cm line+tgl+cond+fsm+branch+assert"
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os.environ["TESTCASE"] = f"{self.test_name}"
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os.environ["MODULE"] = f"caravel_tests"
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os.environ["SIM"] = self.sim_type
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os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
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os.system(f"vcs {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
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self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
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Path(f'{self.sim_path}/{self.passed}').touch()
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os.system("rm AN.DB/ cm.log results.xml ucli.key -rf")
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def find(self,name, path):
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for root, dirs, files in os.walk(path):
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if name in files:
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return os.path.join(root, name)
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print(f"Test {name} doesn't exist or don't have a C file ")
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def test_path(self):
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test_name = self.test_name
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test_name += ".c"
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tests_path = os.path.abspath(f"{self.cocotb_path}/tests")
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test_file = self.find(test_name,tests_path)
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test_path = os.path.dirname(test_file)
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return (test_path)
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def hex_generate(self):
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#open docker
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test_path =self.test_path()
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self.cd_make()
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if not os.path.exists(f"{self.cocotb_path}/hex_files"):
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os.makedirs(f"{self.cocotb_path}/hex_files") # Create a new hex_files directory because it does not exist
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elf_out = f"{self.cocotb_path}/hex_files/{self.test_name}.elf"
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c_file = f"{test_path}/{self.test_name}.c"
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hex_file = f"{self.cocotb_path}/hex_files/{self.test_name}.hex"
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GCC_PATH = "/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937/bin/"
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GCC_PREFIX = "riscv32-unknown-linux-gnu"
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SOURCE_FILES = f"{os.getenv('FIRMWARE_PATH')}/crt0_vex.S {os.getenv('FIRMWARE_PATH')}/isr.c"
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LINKER_SCRIPT = f"{os.getenv('FIRMWARE_PATH')}/sections.lds"
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CPUFLAGS = f"-march=rv32i -mabi=ilp32 -D__vexriscv__ "
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verilog_path = f"{os.getenv('VERILOG_PATH')}"
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test_dir = f"{os.getenv('VERILOG_PATH')}/dv/tests-caravel/mem" # linker script include // TODO: to fix this in the future from the mgmt repo
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print(test_dir)
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elf_command = (f"{GCC_PATH}/{GCC_PREFIX}-gcc -g -I{verilog_path}/dv/firmware -I{verilog_path}/dv/generated -I{verilog_path}/dv/ "
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f"-I{verilog_path}/common {CPUFLAGS} -Wl,-Bstatic,-T,{LINKER_SCRIPT},"
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f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}")
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hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} "
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sed_command = f"sed -ie 's/@10/@00/g' {hex_file}"
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hex_gen_state = os.system(f"docker run -it -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)} efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '")
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self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n")
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self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n")
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self.full_terminal.write(os.path.expandvars(sed_command)+"\n"+"\n")
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self.cd_cocotb()
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self.full_terminal.close()
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if hex_gen_state != 0 :
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print(f"fatal: Error when generating hex")
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sys.exit()
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def cd_make(self):
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os.chdir(f"{os.getenv('VERILOG_PATH')}/dv/make")
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def cd_cocotb(self):
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os.chdir(self.cocotb_path)
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class RunRegression:
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def __init__(self,regression,test,type_arg,testlist) -> None:
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self.cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb"
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self.regression_arg = regression
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self.test_arg = test
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self.testlist_arg = testlist
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if type_arg is None:
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type_arg = "RTL"
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self.type_arg = type_arg
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self.write_command_log()
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with open('tests.json') as f:
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self.tests_json = json.load(f)
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self.tests_json = self.tests_json["Tests"]
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self.get_tests()
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self.run_regression()
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def get_tests(self):
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self.tests = collections.defaultdict(lambda : collections.defaultdict(dict)) #key is testname and value is list of sim types
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self.unknown_tests = 0
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self.passed_tests = 0
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self.failed_tests = 0
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# regression
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if self.regression_arg is not None:
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sim_types = ("RTL","GL","GL_SDF")
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for test,test_elements in self.tests_json.items():
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if fnmatch(test,"_*"):
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continue
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for sim_type in sim_types:
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if self.regression_arg in test_elements[sim_type]:
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self.add_new_test(test_name=test,sim_type = sim_type)
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if (len(self.tests)==0):
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print(f"fatal:{self.regression_arg} is not a valid regression name please input a valid regression \ncheck tests.json for more info")
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sys.exit()
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#test
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if self.test_arg is not None:
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if isinstance(self.test_arg,list):
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for test in self.test_arg:
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if test in self.tests_json:
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if isinstance(self.type_arg,list):
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for sim_type in self.type_arg:
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self.add_new_test(test_name=test,sim_type = sim_type)
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else:
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self.add_new_test(test_name=test,sim_type = self.type_arg)
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else:
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if self.test_arg in self.tests_json:
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if isinstance(self.type_arg,list):
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for sim_type in self.type_arg:
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self.add_new_test(test_name=self.test_arg,sim_type = sim_type)
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else:
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self.add_new_test(test_name=self.test_arg,sim_type = self.type_arg)
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# testlist TODO: add logic for test list
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if self.testlist_arg is not None:
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print(f'fatal: code for test list isnt added yet')
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sys.exit()
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self.update_reg_log()
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def add_new_test(self,test_name,sim_type):
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self.tests[test_name][sim_type]["status"]= "pending"
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self.tests[test_name][sim_type]["starttime"]= "-"
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self.tests[test_name][sim_type]["endtime"]= "-"
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self.tests[test_name][sim_type]["duration"] = "-"
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self.tests[test_name][sim_type]["pass"]= "-"
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self.unknown_tests +=1
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def run_regression(self):
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for test,sim_types in self.tests.items():
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for sim_type,status in sim_types.items(): # TODO: add multithreading or multiprocessing here
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start_time = datetime.now()
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self.tests[test][sim_type]["starttime"] = datetime.now().strftime("%H:%M:%S(%a)")
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self.tests[test][sim_type]["duration"] = "-"
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self.tests[test][sim_type]["status"] = "running"
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self.update_reg_log()
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test_run = RunTest(test,sim_type)
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self.tests[test][sim_type]["status"] = "done"
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self.tests[test][sim_type]["endtime"] = datetime.now().strftime("%H:%M:%S(%a)")
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self.tests[test][sim_type]["duration"] = ("%.10s" % (datetime.now() - start_time))
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self.tests[test][sim_type]["pass"]= test_run.passed
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if test_run.passed == "passed":
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self.passed_tests +=1
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elif test_run.passed == "failed":
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self.failed_tests +=1
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self.unknown_tests -=1
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self.update_reg_log()
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if coverage:
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self.generate_cov()
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#TODO: add send mail here
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def generate_cov(self):
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os.chdir(f"{self.cocotb_path}/sim/{os.getenv('RUNTAG')}")
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os.system(f"urg -dir RTL*/*.vdb -format both -show tests -report coverageRTL/")
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os.system(f"urg -dir GL*/*.vdb -format both -show tests -report coverageGL/")
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os.system(f"urg -dir SDF*/*.vdb -format both -show tests -report coverageSDF/")
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os.chdir(self.cocotb_path)
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def update_reg_log(self):
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file_name=f"sim/{os.getenv('RUNTAG')}/runs.log"
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f = open(file_name, "w")
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f.write(f"{'Test':<25} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
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for test,sim_types in self.tests.items():
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for sim_type,status in sim_types.items():
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new_test_name= f"{sim_type}-{test}"
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f.write(f"{new_test_name:<25} {status['status']:<10} {status['starttime']:<15} {status['endtime']:<15} {status['duration']:<13} {status['pass']:<5}\n")
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f.write(f"\n\nTotal: ({self.passed_tests})passed ({self.failed_tests})failed ({self.unknown_tests})unknown ")
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f.close()
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def write_command_log(self):
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file_name=f"sim/{os.getenv('RUNTAG')}/command.log"
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f = open(file_name, "w")
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f.write(f"{' '.join(sys.argv)}")
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f.close()
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class main():
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def __init__(self,args) -> None:
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self.regression = args.regression
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self.test = args.test
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self.testlist = args.testlist
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self.type = args.sim
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self.tag = args.tag
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self.maxerr = args.maxerr
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self.check_valid_args()
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self.set_tag()
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self.def_env_vars()
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RunRegression(self.regression,self.test,self.type,self.testlist)
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def check_valid_args(self):
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if all(v is None for v in [self.regression, self.test, self.testlist]):
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print ("Fatal: Should provide at least one of the following options regression, test or testlist for more info use --help")
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sys.exit()
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if not set(self.type).issubset(["RTL","GL","GL_SDF"]):
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print (f"Fatal: {self.type} isnt a correct type for -sim it should be one or combination of the following RTL, GL or GL_SDF")
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sys.exit()
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def set_tag(self):
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self.TAG = None # tag will be set in the main phase and other functions will use it
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if self.tag is not None:
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self.TAG = self.tag
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elif self.regression is not None:
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self.TAG = f'{self.regression}_{datetime.now().strftime("%H_%M_%S_%d_%m")}'
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else:
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self.TAG = f'run{random.randint(0,1000)}_{datetime.now().strftime("%H_%M_%S_%d_%m")}'
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Path(f"sim/{self.TAG}").mkdir(parents=True, exist_ok=True)
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print(f"Run tag: {self.TAG}")
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def def_env_vars(self):
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if os.getenv('CARAVEL_ROOT') is None or os.getenv('MCW_ROOT') is None:
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print(f"Fatal: CARAVEL_ROOT or MCW_ROOT are not defined")
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sys.exit()
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cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb"
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os.environ["CARAVEL_VERILOG_PATH"] = f"{os.getenv('CARAVEL_ROOT')}/verilog"
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os.environ["VERILOG_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog"
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os.environ["CARAVEL_PATH"] = f"{os.getenv('CARAVEL_VERILOG_PATH')}"
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os.environ["FIRMWARE_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog/dv/firmware"
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os.environ["RUNTAG"] = f"{self.TAG}"
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os.environ["ERRORMAX"] = f"{self.maxerr}"
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import argparse
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parser = argparse.ArgumentParser(description='Run cocotb tests')
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parser.add_argument('-regression','-r', help='name of regression can found in tests.json')
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parser.add_argument('-test','-t', nargs='+' ,help='name of test if no --sim provided RTL will be run <takes list as input>')
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parser.add_argument('-sim', nargs='+' ,help='Simulation type to be run RTL,GL&GL_SDF provided only when run -test <takes list as input>')
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parser.add_argument('-testlist','-tl', help='path of testlist to be run ')
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parser.add_argument('-tag', help='provide tag of the run default would be regression name and if no regression is provided would be run_<random float>_<timestamp>_')
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parser.add_argument('-maxerr', help='max number of errors for every test before simulation breaks default = 3')
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parser.add_argument('-vcs','-v',action='store_true', help='use vcs as compiler if not used iverilog would be used')
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parser.add_argument('-cov','-c',action='store_true', help='enable code coverage')
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args = parser.parse_args()
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if (args.vcs) :
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iverilog = False
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vcs = True
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if args.cov:
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coverage = True
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if args.sim == None:
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args.sim= ["RTL"]
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print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}")
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main(args)
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