mirror of https://github.com/efabless/caravel.git
2694 lines
211 KiB
Plaintext
2694 lines
211 KiB
Plaintext
|
|
Circuit 1 cell sky130_fd_pr__pfet_01v8_hvt and Circuit 2 cell sky130_fd_pr__pfet_01v8_hvt are black boxes.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt
|
|
-------------------------------------------|-------------------------------------------
|
|
1 |1
|
|
2 |2
|
|
3 |3
|
|
4 |4
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent.
|
|
|
|
Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
|
|
-------------------------------------------|-------------------------------------------
|
|
1 |1
|
|
2 |2
|
|
3 |3
|
|
4 |4
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
|
|
|
|
Circuit 1 cell sky130_fd_pr__pfet_g5v0d10v5 and Circuit 2 cell sky130_fd_pr__pfet_g5v0d10v5 are black boxes.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_pr__pfet_g5v0d10v5 |Circuit 2: sky130_fd_pr__pfet_g5v0d10v5
|
|
-------------------------------------------|-------------------------------------------
|
|
1 |1
|
|
2 |2
|
|
3 |3
|
|
4 |4
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_pr__pfet_g5v0d10v5 and sky130_fd_pr__pfet_g5v0d10v5 are equivalent.
|
|
|
|
Circuit 1 cell sky130_fd_pr__nfet_g5v0d10v5 and Circuit 2 cell sky130_fd_pr__nfet_g5v0d10v5 are black boxes.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_pr__nfet_g5v0d10v5 |Circuit 2: sky130_fd_pr__nfet_g5v0d10v5
|
|
-------------------------------------------|-------------------------------------------
|
|
1 |1
|
|
2 |2
|
|
3 |3
|
|
4 |4
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_pr__nfet_g5v0d10v5 and sky130_fd_pr__nfet_g5v0d10v5 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
|
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
|
|
-------------------------------------------|-------------------------------------------
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__decap_12 and sky130_fd_sc_hd__decap_12 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
|
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__decap_4 and sky130_fd_sc_hd__decap_4 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
|
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
|
|
-------------------------------------------|-------------------------------------------
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
|
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
|
|
-------------------------------------------|-------------------------------------------
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__decap_6 and sky130_fd_sc_hd__decap_6 are equivalent.
|
|
|
|
Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VPB
|
|
Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VNB
|
|
Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VNB
|
|
Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VPB
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__res_generic_po (2) |sky130_fd_pr__res_generic_po (2)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Resolving automorphisms by property value.
|
|
Resolving automorphisms by pin name.
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
LO |LO
|
|
HI |HI
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VNB |VNB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
|
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
|
|
-------------------------------------------|-------------------------------------------
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__decap_8 and sky130_fd_sc_hd__decap_8 are equivalent.
|
|
|
|
Cell sky130_fd_sc_hvl__conb_1 (0) disconnected node: VNB
|
|
Cell sky130_fd_sc_hvl__conb_1 (0) disconnected node: VPB
|
|
Cell sky130_fd_sc_hvl__conb_1 (1) disconnected node: VNB
|
|
Cell sky130_fd_sc_hvl__conb_1 (1) disconnected node: VPB
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hvl__conb_1 |Circuit 2: sky130_fd_sc_hvl__conb_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__res_generic_po (2) |sky130_fd_pr__res_generic_po (2)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Resolving automorphisms by property value.
|
|
Resolving automorphisms by pin name.
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hvl__conb_1 |Circuit 2: sky130_fd_sc_hvl__conb_1
|
|
-------------------------------------------|-------------------------------------------
|
|
HI |HI
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
LO |LO
|
|
VNB |VNB
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hvl__conb_1 and sky130_fd_sc_hvl__conb_1 are equivalent.
|
|
|
|
Class sky130_fd_sc_hvl__lsbufhv2lv_1 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hvl__lsbufhv2lv_1 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hvl__lsbufhv2lv_1 |Circuit 2: sky130_fd_sc_hvl__lsbufhv2lv_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_g5v0d10v5 (2) |sky130_fd_pr__pfet_g5v0d10v5 (2)
|
|
sky130_fd_pr__nfet_g5v0d10v5 (10->4) |sky130_fd_pr__nfet_g5v0d10v5 (10->4)
|
|
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
|
|
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
|
Number of devices: 10 |Number of devices: 10
|
|
Number of nets: 13 **Mismatch** |Number of nets: 11 **Mismatch**
|
|
---------------------------------------------------------------------------------------
|
|
NET mismatches: Class fragments follow (with fanout counts):
|
|
Circuit 1: sky130_fd_sc_hvl__lsbufhv2lv_1 |Circuit 2: sky130_fd_sc_hvl__lsbufhv2lv_1
|
|
|
|
---------------------------------------------------------------------------------------
|
|
Net: a_30_1337# |Net: a_30_1337#
|
|
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1
|
|
sky130_fd_pr__nfet_g5v0d10v5/2 = 2 | sky130_fd_pr__nfet_g5v0d10v5/2 = 2
|
|
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
|
|
sky130_fd_pr__pfet_g5v0d10v5/2 = 1 | sky130_fd_pr__pfet_g5v0d10v5/2 = 1
|
|
|
|
|
Net: VGND_uq0 |Net: VGND
|
|
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 2 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 4
|
|
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
|
|
|
|
|
Net: VNB |Net: VNB
|
|
sky130_fd_pr__nfet_g5v0d10v5/4 = 4 | sky130_fd_pr__nfet_g5v0d10v5/4 = 4
|
|
sky130_fd_pr__nfet_01v8/4 = 1 | sky130_fd_pr__nfet_01v8/4 = 1
|
|
|
|
|
Net: a_30_207# |Net: a_30_207#
|
|
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
|
|
sky130_fd_pr__nfet_g5v0d10v5/2 = 1 | sky130_fd_pr__nfet_g5v0d10v5/2 = 1
|
|
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1
|
|
|
|
|
Net: a_389_1337# |Net: a_389_1337#
|
|
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
|
|
sky130_fd_pr__pfet_01v8_hvt/2 = 1 | sky130_fd_pr__pfet_01v8_hvt/2 = 1
|
|
sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1 | sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1
|
|
---------------------------------------------------------------------------------------
|
|
|
|
---------------------------------------------------------------------------------------
|
|
Net: VPWR_uq0 |(no matching net)
|
|
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 |
|
|
|
|
|
Net: VPWR |(no matching net)
|
|
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 |
|
|
---------------------------------------------------------------------------------------
|
|
|
|
---------------------------------------------------------------------------------------
|
|
Net: A |Net: A
|
|
sky130_fd_pr__pfet_g5v0d10v5/2 = 1 | sky130_fd_pr__pfet_g5v0d10v5/2 = 1
|
|
sky130_fd_pr__nfet_g5v0d10v5/2 = 1 | sky130_fd_pr__nfet_g5v0d10v5/2 = 1
|
|
|
|
|
Net: VPB |Net: VPB
|
|
sky130_fd_pr__pfet_g5v0d10v5/4 = 2 | sky130_fd_pr__pfet_g5v0d10v5/4 = 2
|
|
|
|
|
Net: VGND |Net: VPWR
|
|
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 2 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 2
|
|
---------------------------------------------------------------------------------------
|
|
DEVICE mismatches: Class fragments follow (with node fanout counts):
|
|
Circuit 1: sky130_fd_sc_hvl__lsbufhv2lv_1 |Circuit 2: sky130_fd_sc_hvl__lsbufhv2lv_1
|
|
|
|
---------------------------------------------------------------------------------------
|
|
Instance: sky130_fd_pr__nfet_g5v0d10v5:1 |Instance: sky130_fd_pr__nfet_g5v0d10v5:11
|
|
(1,3) = (3,3) | (1,3) = (5,5)
|
|
2 = 5 | 2 = 2
|
|
4 = 5 | 4 = 5
|
|
|
|
|
Instance: sky130_fd_pr__nfet_g5v0d10v5:6 |Instance: sky130_fd_pr__nfet_g5v0d10v5:3
|
|
(1,3) = (5,2) | (1,3) = (5,3)
|
|
2 = 2 | 2 = 5
|
|
4 = 5 | 4 = 5
|
|
|
|
|
Instance: sky130_fd_pr__nfet_g5v0d10v5:4 |Instance: sky130_fd_pr__nfet_g5v0d10v5:0
|
|
(1,3) = (3,2) | (1,3) = (5,3)
|
|
2 = 5 | 2 = 5
|
|
4 = 5 | 4 = 5
|
|
---------------------------------------------------------------------------------------
|
|
|
|
---------------------------------------------------------------------------------------
|
|
Instance: sky130_fd_pr__pfet_g5v0d10v5:14 |Instance: sky130_fd_pr__pfet_g5v0d10v5:10
|
|
(1,3) = (3,1) | (1,3) = (5,2)
|
|
2 = 5 | 2 = 2
|
|
4 = 2 | 4 = 2
|
|
|
|
|
Instance: sky130_fd_pr__pfet_g5v0d10v5:0 |Instance: sky130_fd_pr__pfet_g5v0d10v5:1
|
|
(1,3) = (5,1) | (1,3) = (3,2)
|
|
2 = 2 | 2 = 5
|
|
4 = 2 | 4 = 2
|
|
---------------------------------------------------------------------------------------
|
|
Netlists do not match.
|
|
Flattening non-matched subcircuits sky130_fd_sc_hvl__lsbufhv2lv_1 sky130_fd_sc_hvl__lsbufhv2lv_1
|
|
|
|
Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VGND
|
|
Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPWR
|
|
Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPB
|
|
Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VGND
|
|
Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPB
|
|
Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPWR
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__diode_pw2nd_05v5 (1) |sky130_fd_pr__diode_pw2nd_05v5 (1)
|
|
Number of devices: 1 |Number of devices: 1
|
|
Number of nets: 2 |Number of nets: 2
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VNB |VNB
|
|
DIODE |DIODE
|
|
VGND |VGND
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_ef_sc_hd__decap_12 |Circuit 2: sky130_ef_sc_hd__decap_12
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
|
|
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_ef_sc_hd__decap_12 |Circuit 2: sky130_ef_sc_hd__decap_12
|
|
-------------------------------------------|-------------------------------------------
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_ef_sc_hd__decap_12 and sky130_ef_sc_hd__decap_12 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__buf_6 (0): Merged 12 parallel devices.
|
|
Class sky130_fd_sc_hd__buf_6 (1): Merged 12 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
|
|
sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
X |X
|
|
VNB |VNB
|
|
A |A
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__buf_6 and sky130_fd_sc_hd__buf_6 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__and2_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__and2_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
|
|
sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
|
|
Number of devices: 6 |Number of devices: 6
|
|
Number of nets: 9 |Number of nets: 9
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4
|
|
-------------------------------------------|-------------------------------------------
|
|
B |B
|
|
A |A
|
|
VGND |VGND
|
|
X |X
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VNB |VNB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and2_4 and sky130_fd_sc_hd__and2_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__and3b_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__and3b_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5)
|
|
sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5)
|
|
Number of devices: 10 |Number of devices: 10
|
|
Number of nets: 12 |Number of nets: 12
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
X |X
|
|
C |C
|
|
B |B
|
|
A_N |A_N
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and3b_4 and sky130_fd_sc_hd__and3b_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__and2_2 (0): Merged 2 parallel devices.
|
|
Class sky130_fd_sc_hd__and2_2 (1): Merged 2 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (4->3) |sky130_fd_pr__pfet_01v8_hvt (4->3)
|
|
sky130_fd_pr__nfet_01v8 (4->3) |sky130_fd_pr__nfet_01v8 (4->3)
|
|
Number of devices: 6 |Number of devices: 6
|
|
Number of nets: 9 |Number of nets: 9
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VNB |VNB
|
|
X |X
|
|
A |A
|
|
B |B
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and2_2 and sky130_fd_sc_hd__and2_2 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__nand2_8 (0): Merged 28 parallel devices.
|
|
Class sky130_fd_sc_hd__nand2_8 (1): Merged 28 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2)
|
|
sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 8 |Number of nets: 8
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8
|
|
-------------------------------------------|-------------------------------------------
|
|
Y |Y
|
|
VGND |VGND
|
|
A |A
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
B |B
|
|
VNB |VNB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__nand2_8 and sky130_fd_sc_hd__nand2_8 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__nand2_2 (0): Merged 4 parallel devices.
|
|
Class sky130_fd_sc_hd__nand2_2 (1): Merged 4 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (4->2) |sky130_fd_pr__pfet_01v8_hvt (4->2)
|
|
sky130_fd_pr__nfet_01v8 (4->2) |sky130_fd_pr__nfet_01v8 (4->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 8 |Number of nets: 8
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
Y |Y
|
|
A |A
|
|
VNB |VNB
|
|
B |B
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__nand2_2 and sky130_fd_sc_hd__nand2_2 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__buf_8 (0): Merged 18 parallel devices.
|
|
Class sky130_fd_sc_hd__buf_8 (1): Merged 18 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (11->2) |sky130_fd_pr__nfet_01v8 (11->2)
|
|
sky130_fd_pr__pfet_01v8_hvt (11->2) |sky130_fd_pr__pfet_01v8_hvt (11->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8
|
|
-------------------------------------------|-------------------------------------------
|
|
X |X
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
A |A
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__buf_8 and sky130_fd_sc_hd__buf_8 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__clkinv_8 (0): Merged 18 parallel devices.
|
|
Class sky130_fd_sc_hd__clkinv_8 (1): Merged 18 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_8 |Circuit 2: sky130_fd_sc_hd__clkinv_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (8->1) |sky130_fd_pr__nfet_01v8 (8->1)
|
|
sky130_fd_pr__pfet_01v8_hvt (12->1) |sky130_fd_pr__pfet_01v8_hvt (12->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_8 |Circuit 2: sky130_fd_sc_hd__clkinv_8
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
VNB |VNB
|
|
Y |Y
|
|
A |A
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkinv_8 and sky130_fd_sc_hd__clkinv_8 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__clkinv_2 (0): Merged 3 parallel devices.
|
|
Class sky130_fd_sc_hd__clkinv_2 (1): Merged 3 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_2 |Circuit 2: sky130_fd_sc_hd__clkinv_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (2->1) |sky130_fd_pr__nfet_01v8 (2->1)
|
|
sky130_fd_pr__pfet_01v8_hvt (3->1) |sky130_fd_pr__pfet_01v8_hvt (3->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_2 |Circuit 2: sky130_fd_sc_hd__clkinv_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
VNB |VNB
|
|
Y |Y
|
|
A |A
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkinv_2 and sky130_fd_sc_hd__clkinv_2 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__clkbuf_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__clkbuf_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
|
|
sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
X |X
|
|
VPB |VPB
|
|
A |A
|
|
VGND |VGND
|
|
VNB |VNB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__buf_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__buf_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
|
|
sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
|
|
-------------------------------------------|-------------------------------------------
|
|
X |X
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
A |A
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__buf_4 and sky130_fd_sc_hd__buf_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__clkinv_4 (0): Merged 8 parallel devices.
|
|
Class sky130_fd_sc_hd__clkinv_4 (1): Merged 8 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_4 |Circuit 2: sky130_fd_sc_hd__clkinv_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (6->1) |sky130_fd_pr__pfet_01v8_hvt (6->1)
|
|
sky130_fd_pr__nfet_01v8 (4->1) |sky130_fd_pr__nfet_01v8 (4->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_4 |Circuit 2: sky130_fd_sc_hd__clkinv_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
VNB |VNB
|
|
A |A
|
|
Y |Y
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkinv_4 and sky130_fd_sc_hd__clkinv_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__and3b_2 (0): Merged 2 parallel devices.
|
|
Class sky130_fd_sc_hd__and3b_2 (1): Merged 2 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
|
|
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
|
|
Number of devices: 10 |Number of devices: 10
|
|
Number of nets: 12 |Number of nets: 12
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
C |C
|
|
X |X
|
|
B |B
|
|
A_N |A_N
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and3b_2 and sky130_fd_sc_hd__and3b_2 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
|
|
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
|
|
Number of devices: 6 |Number of devices: 6
|
|
Number of nets: 9 |Number of nets: 9
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
X |X
|
|
A |A
|
|
B |B
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__nand2_4 (0): Merged 12 parallel devices.
|
|
Class sky130_fd_sc_hd__nand2_4 (1): Merged 12 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_4 |Circuit 2: sky130_fd_sc_hd__nand2_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
|
|
sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 8 |Number of nets: 8
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_4 |Circuit 2: sky130_fd_sc_hd__nand2_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
Y |Y
|
|
A |A
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
B |B
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__nand2_4 and sky130_fd_sc_hd__nand2_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__inv_2 (0): Merged 2 parallel devices.
|
|
Class sky130_fd_sc_hd__inv_2 (1): Merged 2 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (2->1) |sky130_fd_pr__pfet_01v8_hvt (2->1)
|
|
sky130_fd_pr__nfet_01v8 (2->1) |sky130_fd_pr__nfet_01v8 (2->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
Y |Y
|
|
A |A
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__inv_2 and sky130_fd_sc_hd__inv_2 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__clkbuf_8 (0): Merged 16 parallel devices.
|
|
Class sky130_fd_sc_hd__clkbuf_8 (1): Merged 16 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (10->2) |sky130_fd_pr__pfet_01v8_hvt (10->2)
|
|
sky130_fd_pr__nfet_01v8 (10->2) |sky130_fd_pr__nfet_01v8 (10->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
|
|
-------------------------------------------|-------------------------------------------
|
|
X |X
|
|
VGND |VGND
|
|
VNB |VNB
|
|
A |A
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkbuf_8 and sky130_fd_sc_hd__clkbuf_8 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and3b_1 |Circuit 2: sky130_fd_sc_hd__and3b_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
|
|
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
|
|
Number of devices: 10 |Number of devices: 10
|
|
Number of nets: 12 |Number of nets: 12
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and3b_1 |Circuit 2: sky130_fd_sc_hd__and3b_1
|
|
-------------------------------------------|-------------------------------------------
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
X |X
|
|
A_N |A_N
|
|
C |C
|
|
B |B
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and3b_1 and sky130_fd_sc_hd__and3b_1 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_1 |Circuit 2: sky130_fd_sc_hd__nand2_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2)
|
|
sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 8 |Number of nets: 8
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_1 |Circuit 2: sky130_fd_sc_hd__nand2_1
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
Y |Y
|
|
A |A
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
B |B
|
|
VNB |VNB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__nand2_1 and sky130_fd_sc_hd__nand2_1 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__inv_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__inv_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (4->1) |sky130_fd_pr__pfet_01v8_hvt (4->1)
|
|
sky130_fd_pr__nfet_01v8 (4->1) |sky130_fd_pr__nfet_01v8 (4->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
|
|
-------------------------------------------|-------------------------------------------
|
|
Y |Y
|
|
A |A
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__inv_4 and sky130_fd_sc_hd__inv_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__inv_12 (0): Merged 22 parallel devices.
|
|
Class sky130_fd_sc_hd__inv_12 (1): Merged 22 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__inv_12 |Circuit 2: sky130_fd_sc_hd__inv_12
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (12->1) |sky130_fd_pr__pfet_01v8_hvt (12->1)
|
|
sky130_fd_pr__nfet_01v8 (12->1) |sky130_fd_pr__nfet_01v8 (12->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__inv_12 |Circuit 2: sky130_fd_sc_hd__inv_12
|
|
-------------------------------------------|-------------------------------------------
|
|
Y |Y
|
|
A |A
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__inv_12 and sky130_fd_sc_hd__inv_12 are equivalent.
|
|
|
|
Class mprj2_logic_high (0): Merged 44 parallel devices.
|
|
Class mprj2_logic_high (1): Merged 44 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: mprj2_logic_high |Circuit 2: mprj2_logic_high
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_sc_hd__decap_12 (29->1) |sky130_fd_sc_hd__decap_12 (29->1)
|
|
sky130_fd_sc_hd__decap_4 (3->1) |sky130_fd_sc_hd__decap_4 (3->1)
|
|
sky130_fd_sc_hd__decap_3 (15->1) |sky130_fd_sc_hd__decap_3 (15->1)
|
|
sky130_fd_sc_hd__decap_6 (1) |sky130_fd_sc_hd__decap_6 (1)
|
|
sky130_fd_sc_hd__conb_1 (1) |sky130_fd_sc_hd__conb_1 (1)
|
|
Number of devices: 5 |Number of devices: 5
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: mprj2_logic_high |Circuit 2: mprj2_logic_high
|
|
-------------------------------------------|-------------------------------------------
|
|
HI |HI
|
|
vssd2 |vssd2
|
|
vccd2 |vccd2
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes mprj2_logic_high and mprj2_logic_high are equivalent.
|
|
|
|
Class mprj_logic_high (0): Merged 141 parallel devices.
|
|
Class mprj_logic_high (1): Merged 141 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: mprj_logic_high |Circuit 2: mprj_logic_high
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_sc_hd__conb_1 (463) |sky130_fd_sc_hd__conb_1 (463)
|
|
sky130_fd_sc_hd__decap_6 (22->1) |sky130_fd_sc_hd__decap_6 (22->1)
|
|
sky130_fd_sc_hd__decap_12 (89->1) |sky130_fd_sc_hd__decap_12 (89->1)
|
|
sky130_fd_sc_hd__decap_3 (19->1) |sky130_fd_sc_hd__decap_3 (19->1)
|
|
sky130_fd_sc_hd__decap_8 (10->1) |sky130_fd_sc_hd__decap_8 (10->1)
|
|
sky130_fd_sc_hd__decap_4 (6->1) |sky130_fd_sc_hd__decap_4 (6->1)
|
|
Number of devices: 468 |Number of devices: 468
|
|
Number of nets: 928 |Number of nets: 928
|
|
---------------------------------------------------------------------------------------
|
|
Resolving automorphisms by property value.
|
|
Resolving automorphisms by pin name.
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: mprj_logic_high |Circuit 2: mprj_logic_high
|
|
-------------------------------------------|-------------------------------------------
|
|
vssd1 |vssd1
|
|
vccd1 |vccd1
|
|
HI[295] |HI[295]
|
|
HI[462] |HI[462]
|
|
HI[58] |HI[58]
|
|
HI[345] |HI[345]
|
|
HI[178] |HI[178]
|
|
HI[10] |HI[10]
|
|
HI[228] |HI[228]
|
|
HI[130] |HI[130]
|
|
HI[95] |HI[95]
|
|
HI[382] |HI[382]
|
|
HI[432] |HI[432]
|
|
HI[265] |HI[265]
|
|
HI[28] |HI[28]
|
|
HI[315] |HI[315]
|
|
HI[148] |HI[148]
|
|
HI[100] |HI[100]
|
|
HI[65] |HI[65]
|
|
HI[185] |HI[185]
|
|
HI[352] |HI[352]
|
|
HI[235] |HI[235]
|
|
HI[402] |HI[402]
|
|
HI[118] |HI[118]
|
|
HI[272] |HI[272]
|
|
HI[35] |HI[35]
|
|
HI[322] |HI[322]
|
|
HI[155] |HI[155]
|
|
HI[205] |HI[205]
|
|
HI[72] |HI[72]
|
|
HI[192] |HI[192]
|
|
HI[457] |HI[457]
|
|
HI[242] |HI[242]
|
|
HI[125] |HI[125]
|
|
HI[0] |HI[0]
|
|
HI[377] |HI[377]
|
|
HI[42] |HI[42]
|
|
HI[427] |HI[427]
|
|
HI[162] |HI[162]
|
|
HI[212] |HI[212]
|
|
HI[297] |HI[297]
|
|
HI[347] |HI[347]
|
|
HI[12] |HI[12]
|
|
HI[132] |HI[132]
|
|
HI[97] |HI[97]
|
|
HI[384] |HI[384]
|
|
HI[267] |HI[267]
|
|
HI[434] |HI[434]
|
|
HI[317] |HI[317]
|
|
HI[102] |HI[102]
|
|
HI[67] |HI[67]
|
|
HI[187] |HI[187]
|
|
HI[354] |HI[354]
|
|
HI[237] |HI[237]
|
|
HI[404] |HI[404]
|
|
HI[391] |HI[391]
|
|
HI[274] |HI[274]
|
|
HI[441] |HI[441]
|
|
HI[37] |HI[37]
|
|
HI[324] |HI[324]
|
|
HI[157] |HI[157]
|
|
HI[207] |HI[207]
|
|
HI[74] |HI[74]
|
|
HI[194] |HI[194]
|
|
HI[361] |HI[361]
|
|
HI[459] |HI[459]
|
|
HI[244] |HI[244]
|
|
HI[411] |HI[411]
|
|
HI[127] |HI[127]
|
|
HI[281] |HI[281]
|
|
HI[2] |HI[2]
|
|
HI[379] |HI[379]
|
|
HI[44] |HI[44]
|
|
HI[331] |HI[331]
|
|
HI[164] |HI[164]
|
|
HI[429] |HI[429]
|
|
HI[214] |HI[214]
|
|
HI[81] |HI[81]
|
|
HI[299] |HI[299]
|
|
HI[251] |HI[251]
|
|
HI[349] |HI[349]
|
|
HI[14] |HI[14]
|
|
HI[301] |HI[301]
|
|
HI[134] |HI[134]
|
|
HI[99] |HI[99]
|
|
HI[386] |HI[386]
|
|
HI[51] |HI[51]
|
|
HI[269] |HI[269]
|
|
HI[171] |HI[171]
|
|
HI[436] |HI[436]
|
|
HI[319] |HI[319]
|
|
HI[221] |HI[221]
|
|
HI[104] |HI[104]
|
|
HI[69] |HI[69]
|
|
HI[189] |HI[189]
|
|
HI[356] |HI[356]
|
|
HI[21] |HI[21]
|
|
HI[239] |HI[239]
|
|
HI[141] |HI[141]
|
|
HI[406] |HI[406]
|
|
HI[393] |HI[393]
|
|
HI[276] |HI[276]
|
|
HI[443] |HI[443]
|
|
HI[39] |HI[39]
|
|
HI[326] |HI[326]
|
|
HI[159] |HI[159]
|
|
HI[111] |HI[111]
|
|
HI[209] |HI[209]
|
|
HI[76] |HI[76]
|
|
HI[363] |HI[363]
|
|
HI[196] |HI[196]
|
|
HI[246] |HI[246]
|
|
HI[413] |HI[413]
|
|
HI[129] |HI[129]
|
|
HI[4] |HI[4]
|
|
HI[283] |HI[283]
|
|
HI[450] |HI[450]
|
|
HI[46] |HI[46]
|
|
HI[333] |HI[333]
|
|
HI[166] |HI[166]
|
|
HI[216] |HI[216]
|
|
HI[83] |HI[83]
|
|
HI[370] |HI[370]
|
|
HI[253] |HI[253]
|
|
HI[420] |HI[420]
|
|
HI[16] |HI[16]
|
|
HI[303] |HI[303]
|
|
HI[136] |HI[136]
|
|
HI[290] |HI[290]
|
|
HI[388] |HI[388]
|
|
HI[53] |HI[53]
|
|
HI[173] |HI[173]
|
|
HI[340] |HI[340]
|
|
HI[438] |HI[438]
|
|
HI[223] |HI[223]
|
|
HI[90] |HI[90]
|
|
HI[106] |HI[106]
|
|
HI[260] |HI[260]
|
|
HI[358] |HI[358]
|
|
HI[23] |HI[23]
|
|
HI[310] |HI[310]
|
|
HI[143] |HI[143]
|
|
HI[408] |HI[408]
|
|
HI[395] |HI[395]
|
|
HI[60] |HI[60]
|
|
HI[180] |HI[180]
|
|
HI[278] |HI[278]
|
|
HI[445] |HI[445]
|
|
HI[328] |HI[328]
|
|
HI[230] |HI[230]
|
|
HI[113] |HI[113]
|
|
HI[78] |HI[78]
|
|
HI[198] |HI[198]
|
|
HI[365] |HI[365]
|
|
HI[30] |HI[30]
|
|
HI[248] |HI[248]
|
|
HI[150] |HI[150]
|
|
HI[415] |HI[415]
|
|
HI[200] |HI[200]
|
|
HI[285] |HI[285]
|
|
HI[452] |HI[452]
|
|
HI[6] |HI[6]
|
|
HI[48] |HI[48]
|
|
HI[168] |HI[168]
|
|
HI[335] |HI[335]
|
|
HI[218] |HI[218]
|
|
HI[120] |HI[120]
|
|
HI[85] |HI[85]
|
|
HI[372] |HI[372]
|
|
HI[255] |HI[255]
|
|
HI[422] |HI[422]
|
|
HI[18] |HI[18]
|
|
HI[305] |HI[305]
|
|
HI[138] |HI[138]
|
|
HI[292] |HI[292]
|
|
HI[55] |HI[55]
|
|
HI[175] |HI[175]
|
|
HI[342] |HI[342]
|
|
HI[225] |HI[225]
|
|
HI[92] |HI[92]
|
|
HI[108] |HI[108]
|
|
HI[262] |HI[262]
|
|
HI[25] |HI[25]
|
|
HI[312] |HI[312]
|
|
HI[145] |HI[145]
|
|
HI[397] |HI[397]
|
|
HI[62] |HI[62]
|
|
HI[182] |HI[182]
|
|
HI[447] |HI[447]
|
|
HI[232] |HI[232]
|
|
HI[115] |HI[115]
|
|
HI[367] |HI[367]
|
|
HI[32] |HI[32]
|
|
HI[152] |HI[152]
|
|
HI[417] |HI[417]
|
|
HI[202] |HI[202]
|
|
HI[287] |HI[287]
|
|
HI[454] |HI[454]
|
|
HI[8] |HI[8]
|
|
HI[337] |HI[337]
|
|
HI[122] |HI[122]
|
|
HI[87] |HI[87]
|
|
HI[374] |HI[374]
|
|
HI[257] |HI[257]
|
|
HI[424] |HI[424]
|
|
HI[307] |HI[307]
|
|
HI[294] |HI[294]
|
|
HI[461] |HI[461]
|
|
HI[57] |HI[57]
|
|
HI[177] |HI[177]
|
|
HI[344] |HI[344]
|
|
HI[227] |HI[227]
|
|
HI[94] |HI[94]
|
|
HI[381] |HI[381]
|
|
HI[264] |HI[264]
|
|
HI[431] |HI[431]
|
|
HI[27] |HI[27]
|
|
HI[314] |HI[314]
|
|
HI[147] |HI[147]
|
|
HI[399] |HI[399]
|
|
HI[64] |HI[64]
|
|
HI[184] |HI[184]
|
|
HI[449] |HI[449]
|
|
HI[351] |HI[351]
|
|
HI[401] |HI[401]
|
|
HI[234] |HI[234]
|
|
HI[117] |HI[117]
|
|
HI[271] |HI[271]
|
|
HI[369] |HI[369]
|
|
HI[34] |HI[34]
|
|
HI[321] |HI[321]
|
|
HI[154] |HI[154]
|
|
HI[419] |HI[419]
|
|
HI[204] |HI[204]
|
|
HI[71] |HI[71]
|
|
HI[191] |HI[191]
|
|
HI[289] |HI[289]
|
|
HI[456] |HI[456]
|
|
HI[339] |HI[339]
|
|
HI[241] |HI[241]
|
|
HI[124] |HI[124]
|
|
HI[89] |HI[89]
|
|
HI[376] |HI[376]
|
|
HI[41] |HI[41]
|
|
HI[259] |HI[259]
|
|
HI[161] |HI[161]
|
|
HI[426] |HI[426]
|
|
HI[211] |HI[211]
|
|
HI[309] |HI[309]
|
|
HI[296] |HI[296]
|
|
HI[59] |HI[59]
|
|
HI[179] |HI[179]
|
|
HI[346] |HI[346]
|
|
HI[11] |HI[11]
|
|
HI[229] |HI[229]
|
|
HI[131] |HI[131]
|
|
HI[96] |HI[96]
|
|
HI[383] |HI[383]
|
|
HI[266] |HI[266]
|
|
HI[433] |HI[433]
|
|
HI[29] |HI[29]
|
|
HI[316] |HI[316]
|
|
HI[149] |HI[149]
|
|
HI[101] |HI[101]
|
|
HI[66] |HI[66]
|
|
HI[186] |HI[186]
|
|
HI[353] |HI[353]
|
|
HI[236] |HI[236]
|
|
HI[403] |HI[403]
|
|
HI[119] |HI[119]
|
|
HI[390] |HI[390]
|
|
HI[440] |HI[440]
|
|
HI[273] |HI[273]
|
|
HI[36] |HI[36]
|
|
HI[323] |HI[323]
|
|
HI[156] |HI[156]
|
|
HI[206] |HI[206]
|
|
HI[73] |HI[73]
|
|
HI[193] |HI[193]
|
|
HI[360] |HI[360]
|
|
HI[458] |HI[458]
|
|
HI[243] |HI[243]
|
|
HI[410] |HI[410]
|
|
HI[126] |HI[126]
|
|
HI[1] |HI[1]
|
|
HI[280] |HI[280]
|
|
HI[378] |HI[378]
|
|
HI[43] |HI[43]
|
|
HI[163] |HI[163]
|
|
HI[330] |HI[330]
|
|
HI[428] |HI[428]
|
|
HI[213] |HI[213]
|
|
HI[80] |HI[80]
|
|
HI[298] |HI[298]
|
|
HI[250] |HI[250]
|
|
HI[348] |HI[348]
|
|
HI[13] |HI[13]
|
|
HI[300] |HI[300]
|
|
HI[133] |HI[133]
|
|
HI[98] |HI[98]
|
|
HI[385] |HI[385]
|
|
HI[50] |HI[50]
|
|
HI[268] |HI[268]
|
|
HI[435] |HI[435]
|
|
HI[170] |HI[170]
|
|
HI[220] |HI[220]
|
|
HI[318] |HI[318]
|
|
HI[103] |HI[103]
|
|
HI[68] |HI[68]
|
|
HI[188] |HI[188]
|
|
HI[355] |HI[355]
|
|
HI[20] |HI[20]
|
|
HI[238] |HI[238]
|
|
HI[140] |HI[140]
|
|
HI[405] |HI[405]
|
|
HI[392] |HI[392]
|
|
HI[275] |HI[275]
|
|
HI[442] |HI[442]
|
|
HI[38] |HI[38]
|
|
HI[325] |HI[325]
|
|
HI[158] |HI[158]
|
|
HI[208] |HI[208]
|
|
HI[110] |HI[110]
|
|
HI[75] |HI[75]
|
|
HI[195] |HI[195]
|
|
HI[362] |HI[362]
|
|
HI[245] |HI[245]
|
|
HI[412] |HI[412]
|
|
HI[128] |HI[128]
|
|
HI[282] |HI[282]
|
|
HI[3] |HI[3]
|
|
HI[45] |HI[45]
|
|
HI[332] |HI[332]
|
|
HI[165] |HI[165]
|
|
HI[215] |HI[215]
|
|
HI[82] |HI[82]
|
|
HI[252] |HI[252]
|
|
HI[15] |HI[15]
|
|
HI[302] |HI[302]
|
|
HI[135] |HI[135]
|
|
HI[387] |HI[387]
|
|
HI[52] |HI[52]
|
|
HI[172] |HI[172]
|
|
HI[437] |HI[437]
|
|
HI[222] |HI[222]
|
|
HI[105] |HI[105]
|
|
HI[357] |HI[357]
|
|
HI[22] |HI[22]
|
|
HI[142] |HI[142]
|
|
HI[407] |HI[407]
|
|
HI[394] |HI[394]
|
|
HI[277] |HI[277]
|
|
HI[444] |HI[444]
|
|
HI[327] |HI[327]
|
|
HI[112] |HI[112]
|
|
HI[77] |HI[77]
|
|
HI[197] |HI[197]
|
|
HI[364] |HI[364]
|
|
HI[414] |HI[414]
|
|
HI[247] |HI[247]
|
|
HI[284] |HI[284]
|
|
HI[451] |HI[451]
|
|
HI[5] |HI[5]
|
|
HI[47] |HI[47]
|
|
HI[167] |HI[167]
|
|
HI[334] |HI[334]
|
|
HI[217] |HI[217]
|
|
HI[84] |HI[84]
|
|
HI[371] |HI[371]
|
|
HI[254] |HI[254]
|
|
HI[421] |HI[421]
|
|
HI[17] |HI[17]
|
|
HI[304] |HI[304]
|
|
HI[137] |HI[137]
|
|
HI[291] |HI[291]
|
|
HI[389] |HI[389]
|
|
HI[54] |HI[54]
|
|
HI[341] |HI[341]
|
|
HI[174] |HI[174]
|
|
HI[439] |HI[439]
|
|
HI[224] |HI[224]
|
|
HI[91] |HI[91]
|
|
HI[107] |HI[107]
|
|
HI[261] |HI[261]
|
|
HI[359] |HI[359]
|
|
HI[24] |HI[24]
|
|
HI[311] |HI[311]
|
|
HI[409] |HI[409]
|
|
HI[144] |HI[144]
|
|
HI[396] |HI[396]
|
|
HI[61] |HI[61]
|
|
HI[279] |HI[279]
|
|
HI[181] |HI[181]
|
|
HI[446] |HI[446]
|
|
HI[231] |HI[231]
|
|
HI[329] |HI[329]
|
|
HI[114] |HI[114]
|
|
HI[79] |HI[79]
|
|
HI[199] |HI[199]
|
|
HI[366] |HI[366]
|
|
HI[31] |HI[31]
|
|
HI[151] |HI[151]
|
|
HI[249] |HI[249]
|
|
HI[416] |HI[416]
|
|
HI[201] |HI[201]
|
|
HI[453] |HI[453]
|
|
HI[7] |HI[7]
|
|
HI[286] |HI[286]
|
|
HI[49] |HI[49]
|
|
HI[169] |HI[169]
|
|
HI[336] |HI[336]
|
|
HI[219] |HI[219]
|
|
HI[121] |HI[121]
|
|
HI[86] |HI[86]
|
|
HI[373] |HI[373]
|
|
HI[256] |HI[256]
|
|
HI[423] |HI[423]
|
|
HI[19] |HI[19]
|
|
HI[306] |HI[306]
|
|
HI[139] |HI[139]
|
|
HI[293] |HI[293]
|
|
HI[460] |HI[460]
|
|
HI[56] |HI[56]
|
|
HI[176] |HI[176]
|
|
HI[343] |HI[343]
|
|
HI[226] |HI[226]
|
|
HI[93] |HI[93]
|
|
HI[109] |HI[109]
|
|
HI[380] |HI[380]
|
|
HI[263] |HI[263]
|
|
HI[430] |HI[430]
|
|
HI[26] |HI[26]
|
|
HI[313] |HI[313]
|
|
HI[146] |HI[146]
|
|
HI[398] |HI[398]
|
|
HI[63] |HI[63]
|
|
HI[448] |HI[448]
|
|
HI[350] |HI[350]
|
|
HI[183] |HI[183]
|
|
HI[233] |HI[233]
|
|
HI[400] |HI[400]
|
|
HI[116] |HI[116]
|
|
HI[270] |HI[270]
|
|
HI[368] |HI[368]
|
|
HI[33] |HI[33]
|
|
HI[320] |HI[320]
|
|
HI[153] |HI[153]
|
|
HI[418] |HI[418]
|
|
HI[203] |HI[203]
|
|
HI[70] |HI[70]
|
|
HI[190] |HI[190]
|
|
HI[288] |HI[288]
|
|
HI[455] |HI[455]
|
|
HI[9] |HI[9]
|
|
HI[240] |HI[240]
|
|
HI[338] |HI[338]
|
|
HI[123] |HI[123]
|
|
HI[88] |HI[88]
|
|
HI[375] |HI[375]
|
|
HI[40] |HI[40]
|
|
HI[258] |HI[258]
|
|
HI[160] |HI[160]
|
|
HI[425] |HI[425]
|
|
HI[308] |HI[308]
|
|
HI[210] |HI[210]
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes mprj_logic_high and mprj_logic_high are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: mgmt_protect_hv |Circuit 2: mgmt_protect_hv
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_sc_hvl__conb_1 (2) |sky130_fd_sc_hvl__conb_1 (2)
|
|
sky130_fd_pr__pfet_g5v0d10v5 (4) |sky130_fd_pr__pfet_g5v0d10v5 (4)
|
|
sky130_fd_pr__nfet_g5v0d10v5 (20->8) |sky130_fd_pr__nfet_g5v0d10v5 (20->8)
|
|
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
|
|
sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
|
|
Number of devices: 22 |Number of devices: 22
|
|
Number of nets: 20 |Number of nets: 20
|
|
---------------------------------------------------------------------------------------
|
|
Resolving automorphisms by property value.
|
|
Resolving automorphisms by pin name.
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: mgmt_protect_hv |Circuit 2: mgmt_protect_hv
|
|
-------------------------------------------|-------------------------------------------
|
|
vccd |vccd
|
|
vssd |vssd
|
|
vdda2 |vdda2
|
|
vdda1 |vdda1
|
|
vssa2 |vssa2
|
|
vssa1 |vssa1
|
|
mprj2_vdd_logic1 |mprj2_vdd_logic1
|
|
mprj_vdd_logic1 |mprj_vdd_logic1
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes mgmt_protect_hv and mgmt_protect_hv are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__bufbuf_8 (0): Merged 18 parallel devices.
|
|
Class sky130_fd_sc_hd__bufbuf_8 (1): Merged 18 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__bufbuf_8 |Circuit 2: sky130_fd_sc_hd__bufbuf_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (13->4) |sky130_fd_pr__pfet_01v8_hvt (13->4)
|
|
sky130_fd_pr__nfet_01v8 (13->4) |sky130_fd_pr__nfet_01v8 (13->4)
|
|
Number of devices: 8 |Number of devices: 8
|
|
Number of nets: 9 |Number of nets: 9
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__bufbuf_8 |Circuit 2: sky130_fd_sc_hd__bufbuf_8
|
|
-------------------------------------------|-------------------------------------------
|
|
X |X
|
|
A |A
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__bufbuf_8 and sky130_fd_sc_hd__bufbuf_8 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__and2b_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__and2b_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and2b_4 |Circuit 2: sky130_fd_sc_hd__and2b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
|
|
sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
|
|
Number of devices: 8 |Number of devices: 8
|
|
Number of nets: 10 |Number of nets: 10
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and2b_4 |Circuit 2: sky130_fd_sc_hd__and2b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VGND |VGND
|
|
A_N |A_N
|
|
X |X
|
|
B |B
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and2b_4 and sky130_fd_sc_hd__and2b_4 are equivalent.
|
|
|
|
Class mgmt_protect (0): Merged 20502 parallel devices.
|
|
Class mgmt_protect (1): Merged 20502 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: mgmt_protect |Circuit 2: mgmt_protect
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_sc_hd__diode_2 (3590->3181) |sky130_fd_sc_hd__diode_2 (3590->3181)
|
|
sky130_fd_sc_hd__decap_6 (2892->1) |sky130_fd_sc_hd__decap_6 (2892->1)
|
|
sky130_ef_sc_hd__decap_12 (11094->1) |sky130_ef_sc_hd__decap_12 (11094->1)
|
|
sky130_fd_sc_hd__decap_4 (3566->1) |sky130_fd_sc_hd__decap_4 (3566->1)
|
|
sky130_fd_sc_hd__decap_8 (1120->1) |sky130_fd_sc_hd__decap_8 (1120->1)
|
|
sky130_fd_sc_hd__buf_6 (1432) |sky130_fd_sc_hd__buf_6 (1432)
|
|
sky130_fd_sc_hd__decap_3 (1426->1) |sky130_fd_sc_hd__decap_3 (1426->1)
|
|
sky130_fd_sc_hd__and2_4 (211) |sky130_fd_sc_hd__and2_4 (211)
|
|
sky130_fd_sc_hd__and3b_4 (102) |sky130_fd_sc_hd__and3b_4 (102)
|
|
sky130_fd_sc_hd__and2_2 (101) |sky130_fd_sc_hd__and2_2 (101)
|
|
sky130_fd_sc_hd__nand2_8 (51) |sky130_fd_sc_hd__nand2_8 (51)
|
|
sky130_fd_sc_hd__nand2_2 (34) |sky130_fd_sc_hd__nand2_2 (34)
|
|
sky130_fd_sc_hd__buf_8 (559) |sky130_fd_sc_hd__buf_8 (559)
|
|
sky130_fd_sc_hd__clkinv_8 (19) |sky130_fd_sc_hd__clkinv_8 (19)
|
|
sky130_fd_sc_hd__clkinv_2 (44) |sky130_fd_sc_hd__clkinv_2 (44)
|
|
sky130_fd_sc_hd__clkbuf_4 (220) |sky130_fd_sc_hd__clkbuf_4 (220)
|
|
sky130_fd_sc_hd__buf_4 (85) |sky130_fd_sc_hd__buf_4 (85)
|
|
sky130_fd_sc_hd__clkinv_4 (35) |sky130_fd_sc_hd__clkinv_4 (35)
|
|
sky130_fd_sc_hd__and3b_2 (21) |sky130_fd_sc_hd__and3b_2 (21)
|
|
sky130_fd_sc_hd__and2_1 (21) |sky130_fd_sc_hd__and2_1 (21)
|
|
sky130_fd_sc_hd__nand2_4 (66) |sky130_fd_sc_hd__nand2_4 (66)
|
|
sky130_fd_sc_hd__inv_2 (58) |sky130_fd_sc_hd__inv_2 (58)
|
|
sky130_fd_sc_hd__clkbuf_8 (12) |sky130_fd_sc_hd__clkbuf_8 (12)
|
|
sky130_fd_sc_hd__and3b_1 (5) |sky130_fd_sc_hd__and3b_1 (5)
|
|
sky130_fd_sc_hd__nand2_1 (13) |sky130_fd_sc_hd__nand2_1 (13)
|
|
sky130_fd_sc_hd__inv_4 (3) |sky130_fd_sc_hd__inv_4 (3)
|
|
sky130_fd_sc_hd__inv_12 (5) |sky130_fd_sc_hd__inv_12 (5)
|
|
mprj2_logic_high (1) |mprj2_logic_high (1)
|
|
mprj_logic_high (1) |mprj_logic_high (1)
|
|
mgmt_protect_hv (1) |mgmt_protect_hv (1)
|
|
sky130_fd_sc_hd__bufbuf_8 (4) |sky130_fd_sc_hd__bufbuf_8 (4)
|
|
sky130_fd_sc_hd__and2b_4 (1) |sky130_fd_sc_hd__and2b_4 (1)
|
|
Number of devices: 6291 |Number of devices: 6291
|
|
Number of nets: 4204 |Number of nets: 4204
|
|
---------------------------------------------------------------------------------------
|
|
Resolving automorphisms by property value.
|
|
Circuit 2 parallel/series network does not match Circuit 1
|
|
Circuit 1 instance ANTENNA_wire1118_A network:
|
|
M = 1
|
|
M = 1
|
|
Circuit 2 parallel/series network does not match Circuit 1
|
|
Circuit 1 instance ANTENNA_wire1118_A network:
|
|
M = 1
|
|
M = 1
|
|
Circuit 2 parallel/series network does not match Circuit 1
|
|
Circuit 1 instance ANTENNA_wire1118_A network:
|
|
M = 1
|
|
M = 1
|
|
Circuit 2 parallel/series network does not match Circuit 1
|
|
Circuit 1 instance ANTENNA_wire1118_A network:
|
|
M = 1
|
|
M = 1
|
|
Circuit 2 parallel/series network does not match Circuit 1
|
|
Circuit 1 instance ANTENNA_wire1118_A network:
|
|
M = 1
|
|
M = 1
|
|
Resolving automorphisms by pin name.
|
|
Netlists match uniquely with property errors.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: mgmt_protect |Circuit 2: mgmt_protect
|
|
-------------------------------------------|-------------------------------------------
|
|
vccd2_uq0 |vccd2 **Mismatch**
|
|
vssd2 |vssd2
|
|
vccd1_uq1 |vccd1 **Mismatch**
|
|
vssd1_uq2 |vssd1 **Mismatch**
|
|
vdda1_uq0 |vdda1 **Mismatch**
|
|
vdda2_uq0 |vdda2 **Mismatch**
|
|
vssa2_uq0 |vssa2 **Mismatch**
|
|
vssa1_uq0 |vssa1 **Mismatch**
|
|
la_data_in_mprj[23] |la_data_in_mprj[23]
|
|
la_data_in_mprj[7] |la_data_in_mprj[7]
|
|
la_oenb_core[68] |la_oenb_core[68]
|
|
la_data_in_mprj[22] |la_data_in_mprj[22]
|
|
la_data_in_mprj[38] |la_data_in_mprj[38]
|
|
la_oenb_core[36] |la_oenb_core[36]
|
|
la_oenb_core[37] |la_oenb_core[37]
|
|
la_oenb_core[47] |la_oenb_core[47]
|
|
la_oenb_core[78] |la_oenb_core[78]
|
|
mprj_adr_o_user[21] |mprj_adr_o_user[21]
|
|
mprj_adr_o_user[29] |mprj_adr_o_user[29]
|
|
mprj_adr_o_user[28] |mprj_adr_o_user[28]
|
|
mprj_adr_o_user[27] |mprj_adr_o_user[27]
|
|
mprj_adr_o_user[26] |mprj_adr_o_user[26]
|
|
mprj_adr_o_user[25] |mprj_adr_o_user[25]
|
|
mprj_adr_o_user[24] |mprj_adr_o_user[24]
|
|
mprj_adr_o_user[30] |mprj_adr_o_user[30]
|
|
mprj_adr_o_user[31] |mprj_adr_o_user[31]
|
|
mprj_adr_o_user[1] |mprj_adr_o_user[1]
|
|
mprj_adr_o_user[0] |mprj_adr_o_user[0]
|
|
mprj_adr_o_user[5] |mprj_adr_o_user[5]
|
|
mprj_adr_o_user[4] |mprj_adr_o_user[4]
|
|
mprj_adr_o_user[3] |mprj_adr_o_user[3]
|
|
mprj_adr_o_user[2] |mprj_adr_o_user[2]
|
|
la_data_in_mprj[105] |la_data_in_mprj[105]
|
|
la_data_in_mprj[103] |la_data_in_mprj[103]
|
|
la_data_in_mprj[104] |la_data_in_mprj[104]
|
|
la_data_in_mprj[44] |la_data_in_mprj[44]
|
|
la_data_in_mprj[30] |la_data_in_mprj[30]
|
|
la_data_in_mprj[45] |la_data_in_mprj[45]
|
|
la_data_in_mprj[70] |la_data_in_mprj[70]
|
|
la_data_in_mprj[69] |la_data_in_mprj[69]
|
|
la_data_in_mprj[68] |la_data_in_mprj[68]
|
|
la_data_in_mprj[41] |la_data_in_mprj[41]
|
|
la_data_in_mprj[32] |la_data_in_mprj[32]
|
|
la_data_in_mprj[102] |la_data_in_mprj[102]
|
|
la_data_in_mprj[71] |la_data_in_mprj[71]
|
|
la_data_in_mprj[72] |la_data_in_mprj[72]
|
|
la_data_in_mprj[73] |la_data_in_mprj[73]
|
|
la_data_in_mprj[74] |la_data_in_mprj[74]
|
|
la_data_in_mprj[91] |la_data_in_mprj[91]
|
|
la_data_in_mprj[92] |la_data_in_mprj[92]
|
|
la_data_in_mprj[95] |la_data_in_mprj[95]
|
|
la_data_in_mprj[93] |la_data_in_mprj[93]
|
|
la_data_in_mprj[101] |la_data_in_mprj[101]
|
|
la_data_in_mprj[94] |la_data_in_mprj[94]
|
|
user2_vdd_powergood |user2_vdd_powergood
|
|
la_oenb_core[32] |la_oenb_core[32]
|
|
la_oenb_core[35] |la_oenb_core[35]
|
|
la_oenb_core[43] |la_oenb_core[43]
|
|
la_oenb_core[46] |la_oenb_core[46]
|
|
la_oenb_core[48] |la_oenb_core[48]
|
|
user1_vdd_powergood |user1_vdd_powergood
|
|
la_oenb_core[31] |la_oenb_core[31]
|
|
la_oenb_core[40] |la_oenb_core[40]
|
|
user_clock2 |user_clock2
|
|
mprj_sel_o_user[3] |mprj_sel_o_user[3]
|
|
mprj_sel_o_user[2] |mprj_sel_o_user[2]
|
|
mprj_sel_o_user[0] |mprj_sel_o_user[0]
|
|
mprj_sel_o_user[1] |mprj_sel_o_user[1]
|
|
mprj_dat_o_user[22] |mprj_dat_o_user[22]
|
|
mprj_dat_o_user[24] |mprj_dat_o_user[24]
|
|
mprj_dat_o_user[23] |mprj_dat_o_user[23]
|
|
mprj_dat_o_user[31] |mprj_dat_o_user[31]
|
|
mprj_dat_o_user[26] |mprj_dat_o_user[26]
|
|
mprj_dat_o_user[27] |mprj_dat_o_user[27]
|
|
mprj_dat_o_user[25] |mprj_dat_o_user[25]
|
|
mprj_dat_i_core[3] |mprj_dat_i_core[3]
|
|
mprj_dat_o_user[28] |mprj_dat_o_user[28]
|
|
mprj_dat_o_user[29] |mprj_dat_o_user[29]
|
|
mprj_dat_o_user[30] |mprj_dat_o_user[30]
|
|
mprj_dat_i_core[7] |mprj_dat_i_core[7]
|
|
mprj_we_o_user |mprj_we_o_user
|
|
la_data_in_mprj[28] |la_data_in_mprj[28]
|
|
la_data_in_mprj[127] |la_data_in_mprj[127]
|
|
la_data_in_mprj[29] |la_data_in_mprj[29]
|
|
la_data_in_mprj[27] |la_data_in_mprj[27]
|
|
la_data_in_mprj[42] |la_data_in_mprj[42]
|
|
la_data_in_mprj[31] |la_data_in_mprj[31]
|
|
la_data_in_mprj[43] |la_data_in_mprj[43]
|
|
la_data_in_mprj[21] |la_data_in_mprj[21]
|
|
la_data_in_mprj[126] |la_data_in_mprj[126]
|
|
la_data_in_mprj[39] |la_data_in_mprj[39]
|
|
la_data_in_mprj[18] |la_data_in_mprj[18]
|
|
la_data_in_mprj[49] |la_data_in_mprj[49]
|
|
la_data_in_mprj[17] |la_data_in_mprj[17]
|
|
la_data_in_mprj[125] |la_data_in_mprj[125]
|
|
la_data_in_mprj[19] |la_data_in_mprj[19]
|
|
la_data_in_mprj[20] |la_data_in_mprj[20]
|
|
la_data_in_mprj[46] |la_data_in_mprj[46]
|
|
la_data_in_mprj[67] |la_data_in_mprj[67]
|
|
la_data_in_mprj[40] |la_data_in_mprj[40]
|
|
la_data_in_mprj[33] |la_data_in_mprj[33]
|
|
la_data_in_mprj[47] |la_data_in_mprj[47]
|
|
la_data_in_mprj[48] |la_data_in_mprj[48]
|
|
la_data_in_mprj[75] |la_data_in_mprj[75]
|
|
la_data_in_mprj[89] |la_data_in_mprj[89]
|
|
la_data_in_mprj[90] |la_data_in_mprj[90]
|
|
la_data_in_mprj[106] |la_data_in_mprj[106]
|
|
la_data_in_mprj[96] |la_data_in_mprj[96]
|
|
la_data_in_mprj[107] |la_data_in_mprj[107]
|
|
la_data_in_mprj[100] |la_data_in_mprj[100]
|
|
la_data_in_mprj[76] |la_data_in_mprj[76]
|
|
la_data_in_mprj[98] |la_data_in_mprj[98]
|
|
la_data_in_mprj[88] |la_data_in_mprj[88]
|
|
la_data_in_mprj[99] |la_data_in_mprj[99]
|
|
la_data_in_mprj[77] |la_data_in_mprj[77]
|
|
la_data_in_mprj[97] |la_data_in_mprj[97]
|
|
la_data_in_mprj[123] |la_data_in_mprj[123]
|
|
la_data_in_mprj[117] |la_data_in_mprj[117]
|
|
la_data_in_mprj[115] |la_data_in_mprj[115]
|
|
la_data_in_mprj[116] |la_data_in_mprj[116]
|
|
la_data_in_mprj[122] |la_data_in_mprj[122]
|
|
la_data_in_mprj[34] |la_data_in_mprj[34]
|
|
la_data_in_mprj[50] |la_data_in_mprj[50]
|
|
la_data_in_mprj[64] |la_data_in_mprj[64]
|
|
la_data_in_mprj[66] |la_data_in_mprj[66]
|
|
la_oenb_core[102] |la_oenb_core[102]
|
|
la_oenb_core[103] |la_oenb_core[103]
|
|
la_oenb_core[107] |la_oenb_core[107]
|
|
la_oenb_core[106] |la_oenb_core[106]
|
|
la_oenb_core[108] |la_oenb_core[108]
|
|
la_oenb_core[109] |la_oenb_core[109]
|
|
la_oenb_core[110] |la_oenb_core[110]
|
|
la_oenb_core[111] |la_oenb_core[111]
|
|
la_oenb_core[122] |la_oenb_core[122]
|
|
la_oenb_core[101] |la_oenb_core[101]
|
|
la_oenb_core[104] |la_oenb_core[104]
|
|
la_oenb_core[105] |la_oenb_core[105]
|
|
la_oenb_core[123] |la_oenb_core[123]
|
|
la_oenb_core[124] |la_oenb_core[124]
|
|
la_oenb_core[125] |la_oenb_core[125]
|
|
la_oenb_core[27] |la_oenb_core[27]
|
|
la_oenb_core[29] |la_oenb_core[29]
|
|
la_oenb_core[51] |la_oenb_core[51]
|
|
la_oenb_core[54] |la_oenb_core[54]
|
|
la_oenb_core[59] |la_oenb_core[59]
|
|
la_oenb_core[62] |la_oenb_core[62]
|
|
la_oenb_core[100] |la_oenb_core[100]
|
|
la_oenb_core[63] |la_oenb_core[63]
|
|
la_oenb_core[74] |la_oenb_core[74]
|
|
la_oenb_core[73] |la_oenb_core[73]
|
|
la_oenb_core[80] |la_oenb_core[80]
|
|
la_oenb_core[81] |la_oenb_core[81]
|
|
la_oenb_core[72] |la_oenb_core[72]
|
|
la_oenb_core[79] |la_oenb_core[79]
|
|
la_oenb_core[75] |la_oenb_core[75]
|
|
la_oenb_core[76] |la_oenb_core[76]
|
|
la_oenb_core[77] |la_oenb_core[77]
|
|
la_oenb_core[82] |la_oenb_core[82]
|
|
la_oenb_core[83] |la_oenb_core[83]
|
|
la_oenb_core[84] |la_oenb_core[84]
|
|
la_oenb_core[85] |la_oenb_core[85]
|
|
la_oenb_core[86] |la_oenb_core[86]
|
|
la_oenb_core[116] |la_oenb_core[116]
|
|
la_oenb_core[87] |la_oenb_core[87]
|
|
la_oenb_core[88] |la_oenb_core[88]
|
|
la_oenb_core[93] |la_oenb_core[93]
|
|
la_oenb_core[92] |la_oenb_core[92]
|
|
la_oenb_core[64] |la_oenb_core[64]
|
|
la_oenb_core[97] |la_oenb_core[97]
|
|
la_oenb_core[98] |la_oenb_core[98]
|
|
la_oenb_core[94] |la_oenb_core[94]
|
|
la_oenb_core[95] |la_oenb_core[95]
|
|
la_oenb_core[117] |la_oenb_core[117]
|
|
la_oenb_core[113] |la_oenb_core[113]
|
|
la_oenb_core[118] |la_oenb_core[118]
|
|
la_oenb_core[115] |la_oenb_core[115]
|
|
la_oenb_core[114] |la_oenb_core[114]
|
|
la_oenb_core[71] |la_oenb_core[71]
|
|
la_oenb_core[112] |la_oenb_core[112]
|
|
la_oenb_core[121] |la_oenb_core[121]
|
|
la_oenb_core[120] |la_oenb_core[120]
|
|
la_oenb_core[119] |la_oenb_core[119]
|
|
la_oenb_core[96] |la_oenb_core[96]
|
|
la_oenb_core[99] |la_oenb_core[99]
|
|
la_data_in_core[32] |la_data_in_core[32]
|
|
la_data_in_core[100] |la_data_in_core[100]
|
|
la_data_in_core[107] |la_data_in_core[107]
|
|
la_data_in_core[125] |la_data_in_core[125]
|
|
la_data_in_core[33] |la_data_in_core[33]
|
|
la_data_in_core[62] |la_data_in_core[62]
|
|
la_data_in_core[31] |la_data_in_core[31]
|
|
la_data_in_core[30] |la_data_in_core[30]
|
|
la_data_in_core[29] |la_data_in_core[29]
|
|
la_data_in_core[101] |la_data_in_core[101]
|
|
la_data_in_core[124] |la_data_in_core[124]
|
|
la_data_in_core[105] |la_data_in_core[105]
|
|
la_data_in_core[104] |la_data_in_core[104]
|
|
la_data_in_core[123] |la_data_in_core[123]
|
|
la_data_in_core[122] |la_data_in_core[122]
|
|
la_data_in_core[108] |la_data_in_core[108]
|
|
la_data_in_core[106] |la_data_in_core[106]
|
|
la_data_in_core[96] |la_data_in_core[96]
|
|
la_data_in_core[99] |la_data_in_core[99]
|
|
la_oenb_core[61] |la_oenb_core[61]
|
|
la_oenb_core[8] |la_oenb_core[8]
|
|
la_oenb_core[126] |la_oenb_core[126]
|
|
la_oenb_core[57] |la_oenb_core[57]
|
|
la_oenb_core[25] |la_oenb_core[25]
|
|
la_oenb_core[15] |la_oenb_core[15]
|
|
la_oenb_core[7] |la_oenb_core[7]
|
|
la_oenb_core[44] |la_oenb_core[44]
|
|
la_oenb_core[91] |la_oenb_core[91]
|
|
la_oenb_core[12] |la_oenb_core[12]
|
|
mprj_adr_o_user[18] |mprj_adr_o_user[18]
|
|
mprj_cyc_o_user |mprj_cyc_o_user
|
|
la_data_in_core[109] |la_data_in_core[109]
|
|
la_data_in_core[110] |la_data_in_core[110]
|
|
la_data_in_core[111] |la_data_in_core[111]
|
|
la_data_in_core[117] |la_data_in_core[117]
|
|
la_data_in_core[112] |la_data_in_core[112]
|
|
la_data_in_core[120] |la_data_in_core[120]
|
|
la_data_in_core[121] |la_data_in_core[121]
|
|
la_data_in_core[119] |la_data_in_core[119]
|
|
la_data_in_core[65] |la_data_in_core[65]
|
|
la_data_in_core[69] |la_data_in_core[69]
|
|
la_data_in_core[70] |la_data_in_core[70]
|
|
la_data_in_core[67] |la_data_in_core[67]
|
|
la_data_in_core[66] |la_data_in_core[66]
|
|
la_data_in_core[71] |la_data_in_core[71]
|
|
la_data_in_core[64] |la_data_in_core[64]
|
|
la_data_in_core[63] |la_data_in_core[63]
|
|
la_data_in_core[113] |la_data_in_core[113]
|
|
la_data_in_core[118] |la_data_in_core[118]
|
|
la_data_in_core[115] |la_data_in_core[115]
|
|
la_data_in_core[114] |la_data_in_core[114]
|
|
la_data_in_core[73] |la_data_in_core[73]
|
|
la_data_in_core[78] |la_data_in_core[78]
|
|
la_data_in_core[79] |la_data_in_core[79]
|
|
la_data_in_core[77] |la_data_in_core[77]
|
|
la_data_in_core[76] |la_data_in_core[76]
|
|
la_data_in_core[75] |la_data_in_core[75]
|
|
la_data_in_core[74] |la_data_in_core[74]
|
|
la_data_in_core[72] |la_data_in_core[72]
|
|
la_data_in_core[80] |la_data_in_core[80]
|
|
la_data_in_core[81] |la_data_in_core[81]
|
|
la_data_in_core[82] |la_data_in_core[82]
|
|
la_data_in_core[84] |la_data_in_core[84]
|
|
la_data_in_core[83] |la_data_in_core[83]
|
|
la_data_in_core[116] |la_data_in_core[116]
|
|
la_data_in_core[88] |la_data_in_core[88]
|
|
la_data_in_core[87] |la_data_in_core[87]
|
|
la_data_in_core[86] |la_data_in_core[86]
|
|
la_data_in_core[85] |la_data_in_core[85]
|
|
la_data_in_core[98] |la_data_in_core[98]
|
|
la_data_in_core[97] |la_data_in_core[97]
|
|
la_data_in_core[35] |la_data_in_core[35]
|
|
la_data_in_core[13] |la_data_in_core[13]
|
|
la_data_in_core[4] |la_data_in_core[4]
|
|
la_data_in_core[39] |la_data_in_core[39]
|
|
la_data_in_core[51] |la_data_in_core[51]
|
|
la_data_in_core[38] |la_data_in_core[38]
|
|
la_data_in_core[57] |la_data_in_core[57]
|
|
la_data_in_core[37] |la_data_in_core[37]
|
|
la_data_in_core[36] |la_data_in_core[36]
|
|
la_data_in_core[11] |la_data_in_core[11]
|
|
la_data_in_core[17] |la_data_in_core[17]
|
|
la_data_in_core[127] |la_data_in_core[127]
|
|
la_data_in_core[126] |la_data_in_core[126]
|
|
la_data_in_core[42] |la_data_in_core[42]
|
|
la_data_in_core[41] |la_data_in_core[41]
|
|
la_data_in_core[60] |la_data_in_core[60]
|
|
la_data_in_core[50] |la_data_in_core[50]
|
|
la_data_in_core[19] |la_data_in_core[19]
|
|
la_data_in_core[20] |la_data_in_core[20]
|
|
la_data_in_core[93] |la_data_in_core[93]
|
|
la_data_in_core[92] |la_data_in_core[92]
|
|
la_data_in_core[91] |la_data_in_core[91]
|
|
la_data_in_core[90] |la_data_in_core[90]
|
|
la_data_in_core[102] |la_data_in_core[102]
|
|
la_data_in_core[103] |la_data_in_core[103]
|
|
la_data_in_core[12] |la_data_in_core[12]
|
|
la_data_in_core[25] |la_data_in_core[25]
|
|
la_data_in_core[44] |la_data_in_core[44]
|
|
la_data_in_core[34] |la_data_in_core[34]
|
|
la_data_in_core[43] |la_data_in_core[43]
|
|
la_data_in_core[61] |la_data_in_core[61]
|
|
la_data_in_core[40] |la_data_in_core[40]
|
|
la_data_in_core[8] |la_data_in_core[8]
|
|
la_data_in_core[15] |la_data_in_core[15]
|
|
la_data_in_core[7] |la_data_in_core[7]
|
|
la_data_in_core[21] |la_data_in_core[21]
|
|
la_data_in_core[22] |la_data_in_core[22]
|
|
la_data_in_core[24] |la_data_in_core[24]
|
|
la_data_in_core[14] |la_data_in_core[14]
|
|
la_data_in_core[0] |la_data_in_core[0]
|
|
la_data_in_core[5] |la_data_in_core[5]
|
|
la_data_in_core[3] |la_data_in_core[3]
|
|
la_data_in_core[89] |la_data_in_core[89]
|
|
la_data_in_core[59] |la_data_in_core[59]
|
|
la_data_in_core[49] |la_data_in_core[49]
|
|
la_data_in_core[48] |la_data_in_core[48]
|
|
la_data_in_core[28] |la_data_in_core[28]
|
|
la_data_in_core[23] |la_data_in_core[23]
|
|
la_data_in_core[6] |la_data_in_core[6]
|
|
la_data_in_core[2] |la_data_in_core[2]
|
|
la_data_in_core[1] |la_data_in_core[1]
|
|
la_data_in_core[18] |la_data_in_core[18]
|
|
la_data_in_core[47] |la_data_in_core[47]
|
|
la_data_in_core[27] |la_data_in_core[27]
|
|
la_data_in_core[46] |la_data_in_core[46]
|
|
la_data_in_core[45] |la_data_in_core[45]
|
|
la_data_in_core[94] |la_data_in_core[94]
|
|
la_data_in_core[95] |la_data_in_core[95]
|
|
la_data_in_core[16] |la_data_in_core[16]
|
|
la_data_in_core[10] |la_data_in_core[10]
|
|
la_data_in_core[9] |la_data_in_core[9]
|
|
la_oenb_core[60] |la_oenb_core[60]
|
|
la_oenb_core[20] |la_oenb_core[20]
|
|
la_oenb_core[19] |la_oenb_core[19]
|
|
la_oenb_core[38] |la_oenb_core[38]
|
|
la_oenb_core[26] |la_oenb_core[26]
|
|
la_oenb_core[55] |la_oenb_core[55]
|
|
la_oenb_core[45] |la_oenb_core[45]
|
|
la_oenb_core[28] |la_oenb_core[28]
|
|
la_oenb_core[34] |la_oenb_core[34]
|
|
la_oenb_core[33] |la_oenb_core[33]
|
|
la_oenb_core[18] |la_oenb_core[18]
|
|
la_oenb_core[23] |la_oenb_core[23]
|
|
la_oenb_core[2] |la_oenb_core[2]
|
|
la_oenb_core[1] |la_oenb_core[1]
|
|
la_oenb_core[6] |la_oenb_core[6]
|
|
la_oenb_core[42] |la_oenb_core[42]
|
|
la_oenb_core[14] |la_oenb_core[14]
|
|
la_oenb_core[21] |la_oenb_core[21]
|
|
la_oenb_core[22] |la_oenb_core[22]
|
|
la_oenb_core[24] |la_oenb_core[24]
|
|
la_oenb_core[5] |la_oenb_core[5]
|
|
la_oenb_core[0] |la_oenb_core[0]
|
|
la_oenb_core[3] |la_oenb_core[3]
|
|
la_oenb_core[89] |la_oenb_core[89]
|
|
la_oenb_core[127] |la_oenb_core[127]
|
|
la_oenb_core[17] |la_oenb_core[17]
|
|
la_oenb_core[90] |la_oenb_core[90]
|
|
la_oenb_core[11] |la_oenb_core[11]
|
|
la_oenb_core[10] |la_oenb_core[10]
|
|
la_oenb_core[16] |la_oenb_core[16]
|
|
la_oenb_core[9] |la_oenb_core[9]
|
|
mprj_adr_o_user[20] |mprj_adr_o_user[20]
|
|
la_data_in_core[58] |la_data_in_core[58]
|
|
la_data_in_core[26] |la_data_in_core[26]
|
|
la_data_in_core[52] |la_data_in_core[52]
|
|
la_data_in_core[53] |la_data_in_core[53]
|
|
la_data_in_core[54] |la_data_in_core[54]
|
|
la_data_in_core[55] |la_data_in_core[55]
|
|
la_data_in_core[56] |la_data_in_core[56]
|
|
la_oenb_core[41] |la_oenb_core[41]
|
|
la_oenb_core[49] |la_oenb_core[49]
|
|
la_oenb_core[53] |la_oenb_core[53]
|
|
la_oenb_core[56] |la_oenb_core[56]
|
|
mprj_adr_o_user[19] |mprj_adr_o_user[19]
|
|
mprj_adr_o_user[23] |mprj_adr_o_user[23]
|
|
mprj_adr_o_user[7] |mprj_adr_o_user[7]
|
|
mprj_adr_o_user[16] |mprj_adr_o_user[16]
|
|
mprj_adr_o_user[8] |mprj_adr_o_user[8]
|
|
mprj_adr_o_user[15] |mprj_adr_o_user[15]
|
|
la_oenb_core[39] |la_oenb_core[39]
|
|
la_oenb_core[13] |la_oenb_core[13]
|
|
la_oenb_core[4] |la_oenb_core[4]
|
|
mprj_dat_i_core[1] |mprj_dat_i_core[1]
|
|
mprj_dat_i_core[8] |mprj_dat_i_core[8]
|
|
la_oenb_core[58] |la_oenb_core[58]
|
|
mprj_adr_o_user[12] |mprj_adr_o_user[12]
|
|
mprj_adr_o_user[14] |mprj_adr_o_user[14]
|
|
mprj_adr_o_user[17] |mprj_adr_o_user[17]
|
|
mprj_adr_o_user[6] |mprj_adr_o_user[6]
|
|
mprj_adr_o_user[9] |mprj_adr_o_user[9]
|
|
mprj_dat_o_user[2] |mprj_dat_o_user[2]
|
|
mprj_adr_o_user[13] |mprj_adr_o_user[13]
|
|
mprj_adr_o_user[22] |mprj_adr_o_user[22]
|
|
mprj_dat_o_user[1] |mprj_dat_o_user[1]
|
|
mprj_dat_o_user[0] |mprj_dat_o_user[0]
|
|
mprj_adr_o_user[11] |mprj_adr_o_user[11]
|
|
mprj_dat_o_user[3] |mprj_dat_o_user[3]
|
|
mprj_dat_o_user[7] |mprj_dat_o_user[7]
|
|
mprj_dat_o_user[6] |mprj_dat_o_user[6]
|
|
la_oenb_core[50] |la_oenb_core[50]
|
|
la_oenb_core[52] |la_oenb_core[52]
|
|
mprj_adr_o_user[10] |mprj_adr_o_user[10]
|
|
mprj_dat_o_user[4] |mprj_dat_o_user[4]
|
|
mprj_dat_o_user[5] |mprj_dat_o_user[5]
|
|
mprj_dat_o_user[13] |mprj_dat_o_user[13]
|
|
mprj_dat_o_user[14] |mprj_dat_o_user[14]
|
|
mprj_stb_o_user |mprj_stb_o_user
|
|
mprj_dat_o_user[12] |mprj_dat_o_user[12]
|
|
mprj_dat_o_user[11] |mprj_dat_o_user[11]
|
|
mprj_dat_o_user[10] |mprj_dat_o_user[10]
|
|
mprj_dat_o_user[9] |mprj_dat_o_user[9]
|
|
mprj_dat_o_user[8] |mprj_dat_o_user[8]
|
|
mprj_dat_o_user[17] |mprj_dat_o_user[17]
|
|
mprj_dat_o_user[18] |mprj_dat_o_user[18]
|
|
mprj_dat_o_user[19] |mprj_dat_o_user[19]
|
|
mprj_dat_o_user[20] |mprj_dat_o_user[20]
|
|
mprj_dat_o_user[21] |mprj_dat_o_user[21]
|
|
mprj_dat_o_user[15] |mprj_dat_o_user[15]
|
|
mprj_dat_o_user[16] |mprj_dat_o_user[16]
|
|
user1_vcc_powergood |user1_vcc_powergood
|
|
mprj_dat_i_core[23] |mprj_dat_i_core[23]
|
|
mprj_dat_i_core[28] |mprj_dat_i_core[28]
|
|
mprj_dat_i_core[29] |mprj_dat_i_core[29]
|
|
mprj_dat_i_core[30] |mprj_dat_i_core[30]
|
|
mprj_dat_i_core[31] |mprj_dat_i_core[31]
|
|
mprj_dat_i_core[22] |mprj_dat_i_core[22]
|
|
mprj_dat_i_core[25] |mprj_dat_i_core[25]
|
|
mprj_dat_i_core[26] |mprj_dat_i_core[26]
|
|
mprj_dat_i_core[24] |mprj_dat_i_core[24]
|
|
mprj_dat_i_core[27] |mprj_dat_i_core[27]
|
|
mprj_dat_i_core[5] |mprj_dat_i_core[5]
|
|
mprj_dat_i_core[4] |mprj_dat_i_core[4]
|
|
mprj_dat_i_core[6] |mprj_dat_i_core[6]
|
|
mprj_dat_i_core[18] |mprj_dat_i_core[18]
|
|
mprj_dat_i_core[19] |mprj_dat_i_core[19]
|
|
mprj_dat_i_core[2] |mprj_dat_i_core[2]
|
|
mprj_dat_i_core[14] |mprj_dat_i_core[14]
|
|
mprj_dat_i_core[12] |mprj_dat_i_core[12]
|
|
mprj_dat_i_core[13] |mprj_dat_i_core[13]
|
|
mprj_dat_i_core[11] |mprj_dat_i_core[11]
|
|
mprj_dat_i_core[15] |mprj_dat_i_core[15]
|
|
mprj_dat_i_core[16] |mprj_dat_i_core[16]
|
|
mprj_dat_i_core[17] |mprj_dat_i_core[17]
|
|
mprj_dat_i_core[20] |mprj_dat_i_core[20]
|
|
mprj_dat_i_core[21] |mprj_dat_i_core[21]
|
|
mprj_ack_i_core |mprj_dat_i_core[0] **Mismatch**
|
|
mprj_dat_i_core[0] |mprj_ack_i_core **Mismatch**
|
|
mprj_dat_i_core[10] |mprj_dat_i_core[10]
|
|
mprj_dat_i_core[9] |mprj_dat_i_core[9]
|
|
user2_vcc_powergood |user2_vcc_powergood
|
|
user_clock |user_clock
|
|
la_data_in_core[68] |la_data_in_core[68]
|
|
la_data_in_mprj[57] |la_data_in_mprj[57]
|
|
la_data_in_mprj[58] |la_data_in_mprj[58]
|
|
la_data_in_mprj[59] |la_data_in_mprj[59]
|
|
la_data_in_mprj[60] |la_data_in_mprj[60]
|
|
la_data_in_mprj[6] |la_data_in_mprj[6]
|
|
la_data_in_mprj[10] |la_data_in_mprj[10]
|
|
la_data_in_mprj[1] |la_data_in_mprj[1]
|
|
la_data_in_mprj[2] |la_data_in_mprj[2]
|
|
la_data_in_mprj[3] |la_data_in_mprj[3]
|
|
la_data_in_mprj[0] |la_data_in_mprj[0]
|
|
la_data_in_mprj[5] |la_data_in_mprj[5]
|
|
user_reset |user_reset
|
|
la_data_in_mprj[118] |la_data_in_mprj[118]
|
|
la_data_in_mprj[114] |la_data_in_mprj[114]
|
|
la_data_in_mprj[119] |la_data_in_mprj[119]
|
|
la_data_in_mprj[121] |la_data_in_mprj[121]
|
|
la_data_in_mprj[120] |la_data_in_mprj[120]
|
|
la_data_in_mprj[15] |la_data_in_mprj[15]
|
|
la_data_in_mprj[13] |la_data_in_mprj[13]
|
|
la_data_in_mprj[16] |la_data_in_mprj[16]
|
|
la_data_in_mprj[51] |la_data_in_mprj[51]
|
|
la_data_in_mprj[62] |la_data_in_mprj[62]
|
|
la_data_in_mprj[63] |la_data_in_mprj[63]
|
|
la_data_in_mprj[65] |la_data_in_mprj[65]
|
|
la_data_in_mprj[78] |la_data_in_mprj[78]
|
|
la_data_in_mprj[79] |la_data_in_mprj[79]
|
|
la_data_in_mprj[87] |la_data_in_mprj[87]
|
|
la_data_in_mprj[82] |la_data_in_mprj[82]
|
|
la_data_in_mprj[83] |la_data_in_mprj[83]
|
|
la_data_in_mprj[84] |la_data_in_mprj[84]
|
|
la_data_in_mprj[85] |la_data_in_mprj[85]
|
|
la_data_in_mprj[108] |la_data_in_mprj[108]
|
|
la_data_in_mprj[8] |la_data_in_mprj[8]
|
|
la_data_in_mprj[14] |la_data_in_mprj[14]
|
|
la_data_in_mprj[124] |la_data_in_mprj[124]
|
|
la_data_in_mprj[12] |la_data_in_mprj[12]
|
|
la_data_in_mprj[35] |la_data_in_mprj[35]
|
|
la_data_in_mprj[24] |la_data_in_mprj[24]
|
|
la_data_in_mprj[4] |la_data_in_mprj[4]
|
|
la_data_in_mprj[26] |la_data_in_mprj[26]
|
|
la_data_in_mprj[25] |la_data_in_mprj[25]
|
|
user_irq[0] |user_irq[0]
|
|
la_data_in_mprj[36] |la_data_in_mprj[36]
|
|
la_data_in_mprj[37] |la_data_in_mprj[37]
|
|
user_irq[2] |user_irq[2]
|
|
user_irq[1] |user_irq[1]
|
|
la_data_in_mprj[111] |la_data_in_mprj[111]
|
|
la_data_in_mprj[110] |la_data_in_mprj[110]
|
|
la_data_in_mprj[109] |la_data_in_mprj[109]
|
|
la_data_in_mprj[113] |la_data_in_mprj[113]
|
|
la_data_in_mprj[112] |la_data_in_mprj[112]
|
|
la_data_in_mprj[52] |la_data_in_mprj[52]
|
|
la_data_in_mprj[53] |la_data_in_mprj[53]
|
|
la_data_in_mprj[54] |la_data_in_mprj[54]
|
|
la_data_in_mprj[61] |la_data_in_mprj[61]
|
|
la_data_in_mprj[80] |la_data_in_mprj[80]
|
|
la_data_in_mprj[81] |la_data_in_mprj[81]
|
|
la_data_in_mprj[86] |la_data_in_mprj[86]
|
|
la_data_in_mprj[11] |la_data_in_mprj[11]
|
|
la_data_in_mprj[55] |la_data_in_mprj[55]
|
|
la_data_in_mprj[56] |la_data_in_mprj[56]
|
|
la_data_in_mprj[9] |la_data_in_mprj[9]
|
|
la_oenb_core[30] |la_oenb_core[30]
|
|
la_oenb_core[69] |la_oenb_core[69]
|
|
la_oenb_core[65] |la_oenb_core[65]
|
|
la_oenb_core[70] |la_oenb_core[70]
|
|
la_oenb_core[67] |la_oenb_core[67]
|
|
la_oenb_core[66] |la_oenb_core[66]
|
|
la_data_out_core[28] |la_data_out_core[28]
|
|
la_data_out_core[29] |la_data_out_core[29]
|
|
la_data_out_core[27] |la_data_out_core[27]
|
|
la_data_out_core[127] |la_data_out_core[127]
|
|
la_data_out_core[31] |la_data_out_core[31]
|
|
la_data_out_core[43] |la_data_out_core[43]
|
|
la_data_out_core[42] |la_data_out_core[42]
|
|
la_data_out_core[38] |la_data_out_core[38]
|
|
la_data_out_core[22] |la_data_out_core[22]
|
|
la_data_out_core[24] |la_data_out_core[24]
|
|
la_data_out_core[4] |la_data_out_core[4]
|
|
la_data_out_core[23] |la_data_out_core[23]
|
|
la_data_out_core[58] |la_data_out_core[58]
|
|
la_data_out_core[59] |la_data_out_core[59]
|
|
la_data_out_core[60] |la_data_out_core[60]
|
|
la_data_out_core[36] |la_data_out_core[36]
|
|
la_data_out_core[37] |la_data_out_core[37]
|
|
la_data_out_core[26] |la_data_out_core[26]
|
|
user_irq_core[0] |user_irq_core[0]
|
|
la_data_out_core[25] |la_data_out_core[25]
|
|
la_data_out_core[126] |la_data_out_core[126]
|
|
la_data_out_core[61] |la_data_out_core[61]
|
|
la_data_out_core[21] |la_data_out_core[21]
|
|
user_irq_core[2] |user_irq_core[2]
|
|
user_irq_core[1] |user_irq_core[1]
|
|
la_data_out_core[6] |la_data_out_core[6]
|
|
la_data_out_core[10] |la_data_out_core[10]
|
|
la_data_out_core[0] |la_data_out_core[0]
|
|
la_data_out_core[5] |la_data_out_core[5]
|
|
la_data_out_core[1] |la_data_out_core[1]
|
|
la_data_out_core[2] |la_data_out_core[2]
|
|
la_data_out_core[3] |la_data_out_core[3]
|
|
la_data_out_core[13] |la_data_out_core[13]
|
|
la_data_out_core[15] |la_data_out_core[15]
|
|
la_data_out_core[44] |la_data_out_core[44]
|
|
la_data_out_core[52] |la_data_out_core[52]
|
|
la_data_out_core[53] |la_data_out_core[53]
|
|
la_data_out_core[17] |la_data_out_core[17]
|
|
la_data_out_core[125] |la_data_out_core[125]
|
|
la_data_out_core[19] |la_data_out_core[19]
|
|
la_data_out_core[20] |la_data_out_core[20]
|
|
la_data_out_core[67] |la_data_out_core[67]
|
|
la_data_out_core[46] |la_data_out_core[46]
|
|
la_data_out_core[50] |la_data_out_core[50]
|
|
la_data_out_core[64] |la_data_out_core[64]
|
|
la_data_out_core[66] |la_data_out_core[66]
|
|
la_data_out_core[30] |la_data_out_core[30]
|
|
la_data_out_core[45] |la_data_out_core[45]
|
|
la_data_out_core[68] |la_data_out_core[68]
|
|
la_data_out_core[70] |la_data_out_core[70]
|
|
la_data_out_core[69] |la_data_out_core[69]
|
|
la_data_out_core[18] |la_data_out_core[18]
|
|
la_data_out_core[49] |la_data_out_core[49]
|
|
la_data_out_core[16] |la_data_out_core[16]
|
|
la_data_out_core[51] |la_data_out_core[51]
|
|
la_data_out_core[62] |la_data_out_core[62]
|
|
la_data_out_core[63] |la_data_out_core[63]
|
|
la_data_out_core[65] |la_data_out_core[65]
|
|
la_data_out_core[57] |la_data_out_core[57]
|
|
la_data_out_core[12] |la_data_out_core[12]
|
|
la_data_out_core[7] |la_data_out_core[7]
|
|
la_data_out_core[121] |la_data_out_core[121]
|
|
la_data_out_core[122] |la_data_out_core[122]
|
|
la_data_out_core[123] |la_data_out_core[123]
|
|
la_data_out_core[97] |la_data_out_core[97]
|
|
la_data_out_core[77] |la_data_out_core[77]
|
|
la_data_out_core[95] |la_data_out_core[95]
|
|
la_data_out_core[91] |la_data_out_core[91]
|
|
la_data_out_core[92] |la_data_out_core[92]
|
|
la_data_out_core[120] |la_data_out_core[120]
|
|
la_data_out_core[35] |la_data_out_core[35]
|
|
la_data_out_core[88] |la_data_out_core[88]
|
|
la_data_out_core[99] |la_data_out_core[99]
|
|
la_data_out_core[98] |la_data_out_core[98]
|
|
la_data_out_core[9] |la_data_out_core[9]
|
|
la_data_out_core[11] |la_data_out_core[11]
|
|
la_data_out_core[39] |la_data_out_core[39]
|
|
la_data_out_core[78] |la_data_out_core[78]
|
|
la_data_out_core[55] |la_data_out_core[55]
|
|
la_data_out_core[56] |la_data_out_core[56]
|
|
mprj_dat_i_user[12] |mprj_dat_i_user[12]
|
|
mprj_dat_i_user[13] |mprj_dat_i_user[13]
|
|
mprj_dat_i_user[14] |mprj_dat_i_user[14]
|
|
la_data_out_core[105] |la_data_out_core[105]
|
|
mprj_dat_i_user[23] |mprj_dat_i_user[23]
|
|
la_data_out_core[114] |la_data_out_core[114]
|
|
la_data_out_core[118] |la_data_out_core[118]
|
|
la_data_out_core[119] |la_data_out_core[119]
|
|
la_data_out_core[106] |la_data_out_core[106]
|
|
la_data_out_core[96] |la_data_out_core[96]
|
|
la_data_out_core[117] |la_data_out_core[117]
|
|
la_data_out_core[115] |la_data_out_core[115]
|
|
la_data_out_core[116] |la_data_out_core[116]
|
|
la_data_out_core[89] |la_data_out_core[89]
|
|
la_data_out_core[90] |la_data_out_core[90]
|
|
la_data_out_core[113] |la_data_out_core[113]
|
|
la_data_out_core[112] |la_data_out_core[112]
|
|
la_data_out_core[103] |la_data_out_core[103]
|
|
la_data_out_core[104] |la_data_out_core[104]
|
|
la_data_out_core[110] |la_data_out_core[110]
|
|
la_data_out_core[109] |la_data_out_core[109]
|
|
la_data_out_core[111] |la_data_out_core[111]
|
|
la_data_out_core[84] |la_data_out_core[84]
|
|
la_data_out_core[83] |la_data_out_core[83]
|
|
la_data_out_core[82] |la_data_out_core[82]
|
|
la_data_out_core[85] |la_data_out_core[85]
|
|
la_data_out_core[86] |la_data_out_core[86]
|
|
la_data_out_core[81] |la_data_out_core[81]
|
|
la_data_out_core[107] |la_data_out_core[107]
|
|
la_data_out_core[100] |la_data_out_core[100]
|
|
la_data_out_core[76] |la_data_out_core[76]
|
|
la_data_out_core[41] |la_data_out_core[41]
|
|
la_data_out_core[93] |la_data_out_core[93]
|
|
la_data_out_core[40] |la_data_out_core[40]
|
|
la_data_out_core[54] |la_data_out_core[54]
|
|
la_data_out_core[79] |la_data_out_core[79]
|
|
la_data_out_core[80] |la_data_out_core[80]
|
|
la_data_out_core[87] |la_data_out_core[87]
|
|
mprj_dat_i_user[24] |mprj_dat_i_user[24]
|
|
la_data_out_core[14] |la_data_out_core[14]
|
|
la_data_out_core[124] |la_data_out_core[124]
|
|
la_data_out_core[101] |la_data_out_core[101]
|
|
la_data_out_core[94] |la_data_out_core[94]
|
|
la_data_out_core[108] |la_data_out_core[108]
|
|
la_data_out_core[8] |la_data_out_core[8]
|
|
la_data_out_core[32] |la_data_out_core[32]
|
|
la_data_out_core[102] |la_data_out_core[102]
|
|
la_data_out_core[71] |la_data_out_core[71]
|
|
la_data_out_core[72] |la_data_out_core[72]
|
|
la_data_out_core[73] |la_data_out_core[73]
|
|
la_data_out_core[74] |la_data_out_core[74]
|
|
la_data_out_core[33] |la_data_out_core[33]
|
|
la_data_out_core[47] |la_data_out_core[47]
|
|
la_data_out_core[48] |la_data_out_core[48]
|
|
la_data_out_core[75] |la_data_out_core[75]
|
|
la_data_out_core[34] |la_data_out_core[34]
|
|
mprj_dat_i_user[22] |mprj_dat_i_user[22]
|
|
mprj_dat_i_user[25] |mprj_dat_i_user[25]
|
|
mprj_dat_i_user[26] |mprj_dat_i_user[26]
|
|
mprj_dat_i_user[18] |mprj_dat_i_user[18]
|
|
mprj_dat_i_user[19] |mprj_dat_i_user[19]
|
|
mprj_dat_i_user[2] |mprj_dat_i_user[2]
|
|
mprj_dat_i_user[28] |mprj_dat_i_user[28]
|
|
mprj_dat_i_user[29] |mprj_dat_i_user[29]
|
|
mprj_dat_i_user[30] |mprj_dat_i_user[30]
|
|
mprj_dat_i_user[31] |mprj_dat_i_user[31]
|
|
mprj_dat_i_user[3] |mprj_dat_i_user[3]
|
|
mprj_dat_i_user[27] |mprj_dat_i_user[27]
|
|
mprj_dat_i_user[5] |mprj_dat_i_user[5]
|
|
mprj_dat_i_user[4] |mprj_dat_i_user[4]
|
|
mprj_dat_i_user[6] |mprj_dat_i_user[6]
|
|
mprj_dat_i_user[11] |mprj_dat_i_user[11]
|
|
mprj_dat_i_user[7] |mprj_dat_i_user[7]
|
|
mprj_dat_i_user[15] |mprj_dat_i_user[15]
|
|
mprj_dat_i_user[16] |mprj_dat_i_user[16]
|
|
mprj_dat_i_user[17] |mprj_dat_i_user[17]
|
|
mprj_dat_i_user[20] |mprj_dat_i_user[20]
|
|
mprj_dat_i_user[21] |mprj_dat_i_user[21]
|
|
mprj_dat_i_user[8] |mprj_dat_i_user[8]
|
|
mprj_dat_i_user[10] |mprj_dat_i_user[10]
|
|
mprj_dat_i_user[9] |mprj_dat_i_user[9]
|
|
mprj_dat_i_user[0] |mprj_ack_i_user **Mismatch**
|
|
mprj_ack_i_user |mprj_dat_i_user[0] **Mismatch**
|
|
mprj_dat_i_user[1] |mprj_dat_i_user[1]
|
|
la_oenb_mprj[46] |la_oenb_mprj[46]
|
|
la_oenb_mprj[48] |la_oenb_mprj[48]
|
|
la_oenb_mprj[54] |la_oenb_mprj[54]
|
|
la_oenb_mprj[107] |la_oenb_mprj[107]
|
|
la_oenb_mprj[7] |la_oenb_mprj[7]
|
|
la_oenb_mprj[15] |la_oenb_mprj[15]
|
|
la_oenb_mprj[12] |la_oenb_mprj[12]
|
|
la_oenb_mprj[103] |la_oenb_mprj[103]
|
|
la_oenb_mprj[102] |la_oenb_mprj[102]
|
|
la_oenb_mprj[109] |la_oenb_mprj[109]
|
|
la_oenb_mprj[110] |la_oenb_mprj[110]
|
|
la_oenb_mprj[111] |la_oenb_mprj[111]
|
|
la_oenb_mprj[27] |la_oenb_mprj[27]
|
|
la_oenb_mprj[106] |la_oenb_mprj[106]
|
|
la_oenb_mprj[108] |la_oenb_mprj[108]
|
|
la_oenb_mprj[126] |la_oenb_mprj[126]
|
|
la_oenb_mprj[38] |la_oenb_mprj[38]
|
|
la_oenb_mprj[17] |la_oenb_mprj[17]
|
|
la_oenb_mprj[127] |la_oenb_mprj[127]
|
|
la_oenb_mprj[90] |la_oenb_mprj[90]
|
|
la_oenb_mprj[125] |la_oenb_mprj[125]
|
|
la_oenb_mprj[33] |la_oenb_mprj[33]
|
|
la_oenb_mprj[19] |la_oenb_mprj[19]
|
|
la_oenb_mprj[20] |la_oenb_mprj[20]
|
|
la_oenb_mprj[42] |la_oenb_mprj[42]
|
|
la_oenb_mprj[60] |la_oenb_mprj[60]
|
|
la_oenb_mprj[61] |la_oenb_mprj[61]
|
|
la_oenb_mprj[45] |la_oenb_mprj[45]
|
|
la_oenb_mprj[14] |la_oenb_mprj[14]
|
|
la_oenb_mprj[0] |la_oenb_mprj[0]
|
|
la_oenb_mprj[3] |la_oenb_mprj[3]
|
|
la_oenb_mprj[5] |la_oenb_mprj[5]
|
|
la_oenb_mprj[89] |la_oenb_mprj[89]
|
|
la_oenb_mprj[24] |la_oenb_mprj[24]
|
|
la_oenb_mprj[22] |la_oenb_mprj[22]
|
|
la_oenb_mprj[21] |la_oenb_mprj[21]
|
|
la_oenb_mprj[57] |la_oenb_mprj[57]
|
|
la_oenb_mprj[8] |la_oenb_mprj[8]
|
|
la_oenb_mprj[47] |la_oenb_mprj[47]
|
|
la_oenb_mprj[78] |la_oenb_mprj[78]
|
|
la_oenb_mprj[59] |la_oenb_mprj[59]
|
|
la_oenb_mprj[94] |la_oenb_mprj[94]
|
|
la_oenb_mprj[95] |la_oenb_mprj[95]
|
|
la_oenb_mprj[40] |la_oenb_mprj[40]
|
|
la_oenb_mprj[43] |la_oenb_mprj[43]
|
|
la_oenb_mprj[36] |la_oenb_mprj[36]
|
|
la_oenb_mprj[37] |la_oenb_mprj[37]
|
|
la_oenb_mprj[92] |la_oenb_mprj[92]
|
|
la_oenb_mprj[93] |la_oenb_mprj[93]
|
|
la_oenb_mprj[31] |la_oenb_mprj[31]
|
|
la_oenb_mprj[122] |la_oenb_mprj[122]
|
|
la_oenb_mprj[11] |la_oenb_mprj[11]
|
|
la_oenb_mprj[50] |la_oenb_mprj[50]
|
|
la_oenb_mprj[9] |la_oenb_mprj[9]
|
|
la_oenb_mprj[10] |la_oenb_mprj[10]
|
|
la_oenb_mprj[16] |la_oenb_mprj[16]
|
|
la_oenb_mprj[101] |la_oenb_mprj[101]
|
|
la_oenb_mprj[104] |la_oenb_mprj[104]
|
|
la_oenb_mprj[105] |la_oenb_mprj[105]
|
|
la_oenb_mprj[123] |la_oenb_mprj[123]
|
|
la_oenb_mprj[124] |la_oenb_mprj[124]
|
|
la_oenb_mprj[26] |la_oenb_mprj[26]
|
|
la_oenb_mprj[55] |la_oenb_mprj[55]
|
|
la_oenb_mprj[25] |la_oenb_mprj[25]
|
|
la_oenb_mprj[44] |la_oenb_mprj[44]
|
|
la_oenb_mprj[49] |la_oenb_mprj[49]
|
|
la_oenb_mprj[53] |la_oenb_mprj[53]
|
|
la_oenb_mprj[56] |la_oenb_mprj[56]
|
|
la_oenb_mprj[52] |la_oenb_mprj[52]
|
|
la_oenb_mprj[28] |la_oenb_mprj[28]
|
|
la_oenb_mprj[34] |la_oenb_mprj[34]
|
|
la_oenb_mprj[1] |la_oenb_mprj[1]
|
|
la_oenb_mprj[2] |la_oenb_mprj[2]
|
|
la_oenb_mprj[23] |la_oenb_mprj[23]
|
|
la_oenb_mprj[18] |la_oenb_mprj[18]
|
|
la_oenb_mprj[6] |la_oenb_mprj[6]
|
|
la_oenb_mprj[91] |la_oenb_mprj[91]
|
|
la_oenb_mprj[41] |la_oenb_mprj[41]
|
|
la_iena_mprj[126] |la_iena_mprj[126]
|
|
la_data_out_mprj[52] |la_data_out_mprj[52]
|
|
la_data_out_mprj[53] |la_data_out_mprj[53]
|
|
la_data_out_mprj[54] |la_data_out_mprj[54]
|
|
la_data_out_mprj[55] |la_data_out_mprj[55]
|
|
la_data_out_mprj[56] |la_data_out_mprj[56]
|
|
la_data_out_mprj[110] |la_data_out_mprj[110]
|
|
la_data_out_mprj[111] |la_data_out_mprj[111]
|
|
la_data_out_mprj[120] |la_data_out_mprj[120]
|
|
la_data_out_mprj[119] |la_data_out_mprj[119]
|
|
la_data_out_mprj[121] |la_data_out_mprj[121]
|
|
la_data_out_mprj[79] |la_data_out_mprj[79]
|
|
la_data_out_mprj[77] |la_data_out_mprj[77]
|
|
la_data_out_mprj[76] |la_data_out_mprj[76]
|
|
la_data_out_mprj[75] |la_data_out_mprj[75]
|
|
la_data_out_mprj[74] |la_data_out_mprj[74]
|
|
la_data_out_mprj[72] |la_data_out_mprj[72]
|
|
la_iena_mprj[120] |la_iena_mprj[120]
|
|
la_iena_mprj[21] |la_iena_mprj[21]
|
|
la_iena_mprj[29] |la_iena_mprj[29]
|
|
la_iena_mprj[27] |la_iena_mprj[27]
|
|
la_iena_mprj[127] |la_iena_mprj[127]
|
|
la_iena_mprj[19] |la_iena_mprj[19]
|
|
la_iena_mprj[20] |la_iena_mprj[20]
|
|
la_iena_mprj[125] |la_iena_mprj[125]
|
|
la_iena_mprj[45] |la_iena_mprj[45]
|
|
la_iena_mprj[64] |la_iena_mprj[64]
|
|
la_iena_mprj[66] |la_iena_mprj[66]
|
|
la_iena_mprj[67] |la_iena_mprj[67]
|
|
la_iena_mprj[46] |la_iena_mprj[46]
|
|
la_iena_mprj[70] |la_iena_mprj[70]
|
|
la_iena_mprj[69] |la_iena_mprj[69]
|
|
la_iena_mprj[68] |la_iena_mprj[68]
|
|
la_iena_mprj[18] |la_iena_mprj[18]
|
|
la_iena_mprj[44] |la_iena_mprj[44]
|
|
la_iena_mprj[49] |la_iena_mprj[49]
|
|
la_data_out_mprj[58] |la_data_out_mprj[58]
|
|
la_iena_mprj[101] |la_iena_mprj[101]
|
|
la_iena_mprj[119] |la_iena_mprj[119]
|
|
la_iena_mprj[121] |la_iena_mprj[121]
|
|
la_iena_mprj[122] |la_iena_mprj[122]
|
|
la_iena_mprj[123] |la_iena_mprj[123]
|
|
la_iena_mprj[47] |la_iena_mprj[47]
|
|
mprj_sel_o_core[3] |mprj_sel_o_core[3]
|
|
la_oenb_mprj[30] |la_oenb_mprj[30]
|
|
la_oenb_mprj[32] |la_oenb_mprj[32]
|
|
la_oenb_mprj[35] |la_oenb_mprj[35]
|
|
la_oenb_mprj[51] |la_oenb_mprj[51]
|
|
la_oenb_mprj[58] |la_oenb_mprj[58]
|
|
la_oenb_mprj[100] |la_oenb_mprj[100]
|
|
la_oenb_mprj[29] |la_oenb_mprj[29]
|
|
la_oenb_mprj[62] |la_oenb_mprj[62]
|
|
la_oenb_mprj[66] |la_oenb_mprj[66]
|
|
la_oenb_mprj[67] |la_oenb_mprj[67]
|
|
la_oenb_mprj[70] |la_oenb_mprj[70]
|
|
la_oenb_mprj[117] |la_oenb_mprj[117]
|
|
la_oenb_mprj[63] |la_oenb_mprj[63]
|
|
la_oenb_mprj[97] |la_oenb_mprj[97]
|
|
la_oenb_mprj[98] |la_oenb_mprj[98]
|
|
la_oenb_mprj[112] |la_oenb_mprj[112]
|
|
la_oenb_mprj[120] |la_oenb_mprj[120]
|
|
la_oenb_mprj[119] |la_oenb_mprj[119]
|
|
la_oenb_mprj[121] |la_oenb_mprj[121]
|
|
la_oenb_mprj[113] |la_oenb_mprj[113]
|
|
la_oenb_mprj[114] |la_oenb_mprj[114]
|
|
la_oenb_mprj[115] |la_oenb_mprj[115]
|
|
la_oenb_mprj[118] |la_oenb_mprj[118]
|
|
la_oenb_mprj[64] |la_oenb_mprj[64]
|
|
la_oenb_mprj[71] |la_oenb_mprj[71]
|
|
la_oenb_mprj[96] |la_oenb_mprj[96]
|
|
la_oenb_mprj[99] |la_oenb_mprj[99]
|
|
la_oenb_mprj[73] |la_oenb_mprj[73]
|
|
la_oenb_mprj[80] |la_oenb_mprj[80]
|
|
la_oenb_mprj[81] |la_oenb_mprj[81]
|
|
la_oenb_mprj[72] |la_oenb_mprj[72]
|
|
la_oenb_mprj[74] |la_oenb_mprj[74]
|
|
la_oenb_mprj[75] |la_oenb_mprj[75]
|
|
la_oenb_mprj[76] |la_oenb_mprj[76]
|
|
la_oenb_mprj[77] |la_oenb_mprj[77]
|
|
la_oenb_mprj[79] |la_oenb_mprj[79]
|
|
la_data_out_mprj[65] |la_data_out_mprj[65]
|
|
la_data_out_mprj[66] |la_data_out_mprj[66]
|
|
la_data_out_mprj[67] |la_data_out_mprj[67]
|
|
la_data_out_mprj[70] |la_data_out_mprj[70]
|
|
la_data_out_mprj[81] |la_data_out_mprj[81]
|
|
la_data_out_mprj[80] |la_data_out_mprj[80]
|
|
la_data_out_mprj[113] |la_data_out_mprj[113]
|
|
la_data_out_mprj[114] |la_data_out_mprj[114]
|
|
la_data_out_mprj[115] |la_data_out_mprj[115]
|
|
la_data_out_mprj[118] |la_data_out_mprj[118]
|
|
la_data_out_mprj[63] |la_data_out_mprj[63]
|
|
la_data_out_mprj[64] |la_data_out_mprj[64]
|
|
la_data_out_mprj[71] |la_data_out_mprj[71]
|
|
la_iena_mprj[28] |la_iena_mprj[28]
|
|
mprj_dat_o_core[29] |mprj_dat_o_core[29]
|
|
mprj_dat_o_core[30] |mprj_dat_o_core[30]
|
|
caravel_rstn |caravel_rstn
|
|
mprj_adr_o_core[22] |mprj_adr_o_core[22]
|
|
mprj_adr_o_core[0] |mprj_adr_o_core[0]
|
|
mprj_adr_o_core[31] |mprj_adr_o_core[31]
|
|
mprj_adr_o_core[9] |mprj_adr_o_core[9]
|
|
mprj_adr_o_core[6] |mprj_adr_o_core[6]
|
|
mprj_iena_wb |mprj_iena_wb
|
|
mprj_dat_o_core[10] |mprj_dat_o_core[10]
|
|
mprj_dat_o_core[11] |mprj_dat_o_core[11]
|
|
mprj_dat_o_core[12] |mprj_dat_o_core[12]
|
|
mprj_dat_o_core[14] |mprj_dat_o_core[14]
|
|
mprj_dat_o_core[13] |mprj_dat_o_core[13]
|
|
mprj_dat_o_core[16] |mprj_dat_o_core[16]
|
|
mprj_dat_o_core[15] |mprj_dat_o_core[15]
|
|
mprj_dat_o_core[17] |mprj_dat_o_core[17]
|
|
mprj_dat_o_core[8] |mprj_dat_o_core[8]
|
|
mprj_dat_o_core[9] |mprj_dat_o_core[9]
|
|
mprj_stb_o_core |mprj_stb_o_core
|
|
la_oenb_mprj[68] |la_oenb_mprj[68]
|
|
la_oenb_mprj[69] |la_oenb_mprj[69]
|
|
la_oenb_mprj[65] |la_oenb_mprj[65]
|
|
la_oenb_mprj[84] |la_oenb_mprj[84]
|
|
la_oenb_mprj[88] |la_oenb_mprj[88]
|
|
la_oenb_mprj[116] |la_oenb_mprj[116]
|
|
la_oenb_mprj[86] |la_oenb_mprj[86]
|
|
la_oenb_mprj[85] |la_oenb_mprj[85]
|
|
la_oenb_mprj[87] |la_oenb_mprj[87]
|
|
la_oenb_mprj[83] |la_oenb_mprj[83]
|
|
la_oenb_mprj[82] |la_oenb_mprj[82]
|
|
la_data_out_mprj[68] |la_data_out_mprj[68]
|
|
la_data_out_mprj[69] |la_data_out_mprj[69]
|
|
la_data_out_mprj[83] |la_data_out_mprj[83]
|
|
la_data_out_mprj[84] |la_data_out_mprj[84]
|
|
la_data_out_mprj[116] |la_data_out_mprj[116]
|
|
la_data_out_mprj[85] |la_data_out_mprj[85]
|
|
la_data_out_mprj[86] |la_data_out_mprj[86]
|
|
la_data_out_mprj[87] |la_data_out_mprj[87]
|
|
la_data_out_mprj[88] |la_data_out_mprj[88]
|
|
la_data_out_mprj[82] |la_data_out_mprj[82]
|
|
la_data_out_mprj[117] |la_data_out_mprj[117]
|
|
mprj_dat_o_core[23] |mprj_dat_o_core[23]
|
|
mprj_dat_o_core[24] |mprj_dat_o_core[24]
|
|
mprj_dat_o_core[28] |mprj_dat_o_core[28]
|
|
mprj_dat_o_core[25] |mprj_dat_o_core[25]
|
|
mprj_dat_o_core[27] |mprj_dat_o_core[27]
|
|
mprj_dat_o_core[26] |mprj_dat_o_core[26]
|
|
mprj_dat_o_core[31] |mprj_dat_o_core[31]
|
|
mprj_adr_o_core[13] |mprj_adr_o_core[13]
|
|
mprj_dat_o_core[2] |mprj_dat_o_core[2]
|
|
mprj_adr_o_core[11] |mprj_adr_o_core[11]
|
|
mprj_dat_o_core[3] |mprj_dat_o_core[3]
|
|
mprj_dat_o_core[6] |mprj_dat_o_core[6]
|
|
mprj_dat_o_core[7] |mprj_dat_o_core[7]
|
|
mprj_adr_o_core[10] |mprj_adr_o_core[10]
|
|
mprj_dat_o_core[4] |mprj_dat_o_core[4]
|
|
mprj_dat_o_core[5] |mprj_dat_o_core[5]
|
|
mprj_adr_o_core[14] |mprj_adr_o_core[14]
|
|
mprj_adr_o_core[17] |mprj_adr_o_core[17]
|
|
mprj_adr_o_core[12] |mprj_adr_o_core[12]
|
|
mprj_adr_o_core[20] |mprj_adr_o_core[20]
|
|
mprj_adr_o_core[23] |mprj_adr_o_core[23]
|
|
mprj_adr_o_core[19] |mprj_adr_o_core[19]
|
|
mprj_adr_o_core[18] |mprj_adr_o_core[18]
|
|
mprj_adr_o_core[16] |mprj_adr_o_core[16]
|
|
mprj_adr_o_core[7] |mprj_adr_o_core[7]
|
|
mprj_cyc_o_core |mprj_cyc_o_core
|
|
mprj_adr_o_core[1] |mprj_adr_o_core[1]
|
|
mprj_adr_o_core[2] |mprj_adr_o_core[2]
|
|
mprj_adr_o_core[3] |mprj_adr_o_core[3]
|
|
mprj_adr_o_core[4] |mprj_adr_o_core[4]
|
|
mprj_adr_o_core[5] |mprj_adr_o_core[5]
|
|
mprj_adr_o_core[15] |mprj_adr_o_core[15]
|
|
mprj_adr_o_core[21] |mprj_adr_o_core[21]
|
|
mprj_adr_o_core[8] |mprj_adr_o_core[8]
|
|
mprj_adr_o_core[24] |mprj_adr_o_core[24]
|
|
mprj_adr_o_core[25] |mprj_adr_o_core[25]
|
|
mprj_adr_o_core[26] |mprj_adr_o_core[26]
|
|
mprj_adr_o_core[27] |mprj_adr_o_core[27]
|
|
mprj_adr_o_core[28] |mprj_adr_o_core[28]
|
|
mprj_adr_o_core[29] |mprj_adr_o_core[29]
|
|
mprj_adr_o_core[30] |mprj_adr_o_core[30]
|
|
mprj_dat_o_core[0] |mprj_dat_o_core[0]
|
|
mprj_dat_o_core[1] |mprj_dat_o_core[1]
|
|
mprj_dat_o_core[18] |mprj_dat_o_core[18]
|
|
mprj_dat_o_core[19] |mprj_dat_o_core[19]
|
|
mprj_dat_o_core[20] |mprj_dat_o_core[20]
|
|
mprj_dat_o_core[21] |mprj_dat_o_core[21]
|
|
mprj_dat_o_core[22] |mprj_dat_o_core[22]
|
|
mprj_we_o_core |mprj_we_o_core
|
|
la_data_out_mprj[39] |la_data_out_mprj[39]
|
|
la_data_out_mprj[13] |la_data_out_mprj[13]
|
|
la_data_out_mprj[4] |la_data_out_mprj[4]
|
|
la_iena_mprj[35] |la_iena_mprj[35]
|
|
la_iena_mprj[54] |la_iena_mprj[54]
|
|
la_iena_mprj[55] |la_iena_mprj[55]
|
|
la_iena_mprj[56] |la_iena_mprj[56]
|
|
la_iena_mprj[57] |la_iena_mprj[57]
|
|
la_iena_mprj[77] |la_iena_mprj[77]
|
|
la_iena_mprj[90] |la_iena_mprj[90]
|
|
la_iena_mprj[93] |la_iena_mprj[93]
|
|
la_data_out_mprj[51] |la_data_out_mprj[51]
|
|
la_iena_mprj[4] |la_iena_mprj[4]
|
|
la_iena_mprj[1] |la_iena_mprj[1]
|
|
la_iena_mprj[2] |la_iena_mprj[2]
|
|
la_iena_mprj[3] |la_iena_mprj[3]
|
|
user_irq_ena[1] |user_irq_ena[1]
|
|
la_iena_mprj[10] |la_iena_mprj[10]
|
|
la_iena_mprj[0] |la_iena_mprj[0]
|
|
la_iena_mprj[5] |la_iena_mprj[5]
|
|
la_data_out_mprj[102] |la_data_out_mprj[102]
|
|
la_data_out_mprj[103] |la_data_out_mprj[103]
|
|
la_data_out_mprj[11] |la_data_out_mprj[11]
|
|
la_data_out_mprj[126] |la_data_out_mprj[126]
|
|
la_data_out_mprj[127] |la_data_out_mprj[127]
|
|
la_data_out_mprj[17] |la_data_out_mprj[17]
|
|
la_data_out_mprj[19] |la_data_out_mprj[19]
|
|
la_data_out_mprj[20] |la_data_out_mprj[20]
|
|
la_data_out_mprj[41] |la_data_out_mprj[41]
|
|
la_data_out_mprj[42] |la_data_out_mprj[42]
|
|
la_data_out_mprj[50] |la_data_out_mprj[50]
|
|
la_data_out_mprj[60] |la_data_out_mprj[60]
|
|
la_data_out_mprj[90] |la_data_out_mprj[90]
|
|
la_data_out_mprj[91] |la_data_out_mprj[91]
|
|
la_data_out_mprj[92] |la_data_out_mprj[92]
|
|
la_data_out_mprj[93] |la_data_out_mprj[93]
|
|
la_iena_mprj[13] |la_iena_mprj[13]
|
|
la_iena_mprj[36] |la_iena_mprj[36]
|
|
la_iena_mprj[37] |la_iena_mprj[37]
|
|
la_iena_mprj[38] |la_iena_mprj[38]
|
|
la_iena_mprj[58] |la_iena_mprj[58]
|
|
la_iena_mprj[59] |la_iena_mprj[59]
|
|
la_iena_mprj[60] |la_iena_mprj[60]
|
|
la_iena_mprj[6] |la_iena_mprj[6]
|
|
la_iena_mprj[96] |la_iena_mprj[96]
|
|
la_data_out_mprj[112] |la_data_out_mprj[112]
|
|
caravel_clk |caravel_clk
|
|
caravel_clk2 |caravel_clk2
|
|
la_iena_mprj[117] |la_iena_mprj[117]
|
|
la_iena_mprj[115] |la_iena_mprj[115]
|
|
la_iena_mprj[116] |la_iena_mprj[116]
|
|
la_iena_mprj[111] |la_iena_mprj[111]
|
|
la_iena_mprj[110] |la_iena_mprj[110]
|
|
la_iena_mprj[109] |la_iena_mprj[109]
|
|
la_iena_mprj[34] |la_iena_mprj[34]
|
|
la_iena_mprj[39] |la_iena_mprj[39]
|
|
la_iena_mprj[40] |la_iena_mprj[40]
|
|
la_iena_mprj[41] |la_iena_mprj[41]
|
|
la_iena_mprj[42] |la_iena_mprj[42]
|
|
la_iena_mprj[78] |la_iena_mprj[78]
|
|
la_iena_mprj[7] |la_iena_mprj[7]
|
|
la_iena_mprj[81] |la_iena_mprj[81]
|
|
la_iena_mprj[82] |la_iena_mprj[82]
|
|
la_iena_mprj[83] |la_iena_mprj[83]
|
|
la_iena_mprj[84] |la_iena_mprj[84]
|
|
la_iena_mprj[85] |la_iena_mprj[85]
|
|
la_iena_mprj[86] |la_iena_mprj[86]
|
|
la_iena_mprj[89] |la_iena_mprj[89]
|
|
la_iena_mprj[108] |la_iena_mprj[108]
|
|
la_iena_mprj[8] |la_iena_mprj[8]
|
|
la_iena_mprj[88] |la_iena_mprj[88]
|
|
la_iena_mprj[87] |la_iena_mprj[87]
|
|
la_iena_mprj[92] |la_iena_mprj[92]
|
|
la_iena_mprj[91] |la_iena_mprj[91]
|
|
la_iena_mprj[95] |la_iena_mprj[95]
|
|
la_iena_mprj[9] |la_iena_mprj[9]
|
|
la_data_out_mprj[32] |la_data_out_mprj[32]
|
|
la_iena_mprj[79] |la_iena_mprj[79]
|
|
la_iena_mprj[80] |la_iena_mprj[80]
|
|
la_data_out_mprj[36] |la_data_out_mprj[36]
|
|
la_data_out_mprj[37] |la_data_out_mprj[37]
|
|
la_data_out_mprj[38] |la_data_out_mprj[38]
|
|
la_data_out_mprj[57] |la_data_out_mprj[57]
|
|
la_oenb_mprj[39] |la_oenb_mprj[39]
|
|
la_oenb_mprj[4] |la_oenb_mprj[4]
|
|
la_oenb_mprj[13] |la_oenb_mprj[13]
|
|
la_iena_mprj[15] |la_iena_mprj[15]
|
|
la_data_out_mprj[35] |la_data_out_mprj[35]
|
|
la_iena_mprj[118] |la_iena_mprj[118]
|
|
la_iena_mprj[107] |la_iena_mprj[107]
|
|
la_iena_mprj[113] |la_iena_mprj[113]
|
|
la_iena_mprj[103] |la_iena_mprj[103]
|
|
la_iena_mprj[104] |la_iena_mprj[104]
|
|
la_iena_mprj[112] |la_iena_mprj[112]
|
|
la_iena_mprj[114] |la_iena_mprj[114]
|
|
la_iena_mprj[100] |la_iena_mprj[100]
|
|
la_iena_mprj[31] |la_iena_mprj[31]
|
|
la_iena_mprj[43] |la_iena_mprj[43]
|
|
la_iena_mprj[48] |la_iena_mprj[48]
|
|
la_iena_mprj[71] |la_iena_mprj[71]
|
|
la_iena_mprj[72] |la_iena_mprj[72]
|
|
la_iena_mprj[73] |la_iena_mprj[73]
|
|
la_iena_mprj[74] |la_iena_mprj[74]
|
|
la_iena_mprj[75] |la_iena_mprj[75]
|
|
la_iena_mprj[76] |la_iena_mprj[76]
|
|
la_iena_mprj[94] |la_iena_mprj[94]
|
|
la_iena_mprj[124] |la_iena_mprj[124]
|
|
la_iena_mprj[102] |la_iena_mprj[102]
|
|
la_iena_mprj[32] |la_iena_mprj[32]
|
|
la_iena_mprj[14] |la_iena_mprj[14]
|
|
la_iena_mprj[33] |la_iena_mprj[33]
|
|
la_iena_mprj[12] |la_iena_mprj[12]
|
|
la_iena_mprj[97] |la_iena_mprj[97]
|
|
la_iena_mprj[98] |la_iena_mprj[98]
|
|
la_iena_mprj[11] |la_iena_mprj[11]
|
|
la_iena_mprj[99] |la_iena_mprj[99]
|
|
mprj_sel_o_core[0] |mprj_sel_o_core[0]
|
|
mprj_sel_o_core[1] |mprj_sel_o_core[1]
|
|
la_iena_mprj[61] |la_iena_mprj[61]
|
|
user_irq_ena[0] |user_irq_ena[0]
|
|
la_iena_mprj[26] |la_iena_mprj[26]
|
|
la_iena_mprj[25] |la_iena_mprj[25]
|
|
la_iena_mprj[23] |la_iena_mprj[23]
|
|
user_irq_ena[2] |user_irq_ena[2]
|
|
la_data_out_mprj[109] |la_data_out_mprj[109]
|
|
la_data_out_mprj[12] |la_data_out_mprj[12]
|
|
la_data_out_mprj[25] |la_data_out_mprj[25]
|
|
la_data_out_mprj[27] |la_data_out_mprj[27]
|
|
la_data_out_mprj[28] |la_data_out_mprj[28]
|
|
la_data_out_mprj[34] |la_data_out_mprj[34]
|
|
la_data_out_mprj[40] |la_data_out_mprj[40]
|
|
la_data_out_mprj[43] |la_data_out_mprj[43]
|
|
la_data_out_mprj[44] |la_data_out_mprj[44]
|
|
la_data_out_mprj[45] |la_data_out_mprj[45]
|
|
la_data_out_mprj[46] |la_data_out_mprj[46]
|
|
la_data_out_mprj[47] |la_data_out_mprj[47]
|
|
la_data_out_mprj[48] |la_data_out_mprj[48]
|
|
la_data_out_mprj[49] |la_data_out_mprj[49]
|
|
la_data_out_mprj[59] |la_data_out_mprj[59]
|
|
la_data_out_mprj[61] |la_data_out_mprj[61]
|
|
la_data_out_mprj[23] |la_data_out_mprj[23]
|
|
la_data_out_mprj[18] |la_data_out_mprj[18]
|
|
la_data_out_mprj[1] |la_data_out_mprj[1]
|
|
la_data_out_mprj[2] |la_data_out_mprj[2]
|
|
la_data_out_mprj[6] |la_data_out_mprj[6]
|
|
la_data_out_mprj[73] |la_data_out_mprj[73]
|
|
la_data_out_mprj[78] |la_data_out_mprj[78]
|
|
la_data_out_mprj[15] |la_data_out_mprj[15]
|
|
la_data_out_mprj[7] |la_data_out_mprj[7]
|
|
la_data_out_mprj[21] |la_data_out_mprj[21]
|
|
la_data_out_mprj[89] |la_data_out_mprj[89]
|
|
la_data_out_mprj[0] |la_data_out_mprj[0]
|
|
la_data_out_mprj[14] |la_data_out_mprj[14]
|
|
la_data_out_mprj[3] |la_data_out_mprj[3]
|
|
la_data_out_mprj[5] |la_data_out_mprj[5]
|
|
la_data_out_mprj[22] |la_data_out_mprj[22]
|
|
la_data_out_mprj[24] |la_data_out_mprj[24]
|
|
la_data_out_mprj[8] |la_data_out_mprj[8]
|
|
la_data_out_mprj[95] |la_data_out_mprj[95]
|
|
la_data_out_mprj[94] |la_data_out_mprj[94]
|
|
la_data_out_mprj[98] |la_data_out_mprj[98]
|
|
la_data_out_mprj[97] |la_data_out_mprj[97]
|
|
la_data_out_mprj[10] |la_data_out_mprj[10]
|
|
la_data_out_mprj[16] |la_data_out_mprj[16]
|
|
la_data_out_mprj[9] |la_data_out_mprj[9]
|
|
la_iena_mprj[105] |la_iena_mprj[105]
|
|
la_iena_mprj[106] |la_iena_mprj[106]
|
|
la_iena_mprj[22] |la_iena_mprj[22]
|
|
la_iena_mprj[24] |la_iena_mprj[24]
|
|
la_iena_mprj[30] |la_iena_mprj[30]
|
|
la_iena_mprj[17] |la_iena_mprj[17]
|
|
la_iena_mprj[16] |la_iena_mprj[16]
|
|
la_iena_mprj[50] |la_iena_mprj[50]
|
|
la_iena_mprj[51] |la_iena_mprj[51]
|
|
la_iena_mprj[52] |la_iena_mprj[52]
|
|
la_iena_mprj[53] |la_iena_mprj[53]
|
|
la_iena_mprj[62] |la_iena_mprj[62]
|
|
la_iena_mprj[63] |la_iena_mprj[63]
|
|
la_iena_mprj[65] |la_iena_mprj[65]
|
|
mprj_sel_o_core[2] |mprj_sel_o_core[2]
|
|
la_data_out_mprj[100] |la_data_out_mprj[100]
|
|
la_data_out_mprj[107] |la_data_out_mprj[107]
|
|
la_data_out_mprj[125] |la_data_out_mprj[125]
|
|
la_data_out_mprj[26] |la_data_out_mprj[26]
|
|
la_data_out_mprj[101] |la_data_out_mprj[101]
|
|
la_data_out_mprj[104] |la_data_out_mprj[104]
|
|
la_data_out_mprj[105] |la_data_out_mprj[105]
|
|
la_data_out_mprj[123] |la_data_out_mprj[123]
|
|
la_data_out_mprj[124] |la_data_out_mprj[124]
|
|
la_data_out_mprj[29] |la_data_out_mprj[29]
|
|
la_data_out_mprj[30] |la_data_out_mprj[30]
|
|
la_data_out_mprj[31] |la_data_out_mprj[31]
|
|
la_data_out_mprj[33] |la_data_out_mprj[33]
|
|
la_data_out_mprj[62] |la_data_out_mprj[62]
|
|
la_data_out_mprj[106] |la_data_out_mprj[106]
|
|
la_data_out_mprj[108] |la_data_out_mprj[108]
|
|
la_data_out_mprj[122] |la_data_out_mprj[122]
|
|
la_data_out_mprj[99] |la_data_out_mprj[99]
|
|
la_data_out_mprj[96] |la_data_out_mprj[96]
|
|
vssd |vssd
|
|
vccd |vccd
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists for mgmt_protect and mgmt_protect altered to match.
|
|
Device classes mgmt_protect and mgmt_protect are equivalent.
|
|
|
|
Final result: Top level cell failed pin matching.
|
|
|
|
The following cells had property errors:
|
|
mgmt_protect
|