mirror of https://github.com/efabless/caravel.git
292 lines
16 KiB
Modula-2
292 lines
16 KiB
Modula-2
VERSION 5.8 ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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DESIGN gpio_defaults_block ;
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UNITS DISTANCE MICRONS 1000 ;
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DIEAREA ( 0 0 ) ( 17000 28000 ) ;
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ROW ROW_0 unithd 2300 5440 N DO 30 BY 1 STEP 460 0 ;
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ROW ROW_1 unithd 2300 8160 FS DO 30 BY 1 STEP 460 0 ;
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ROW ROW_2 unithd 2300 10880 N DO 30 BY 1 STEP 460 0 ;
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ROW ROW_3 unithd 2300 13600 FS DO 30 BY 1 STEP 460 0 ;
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ROW ROW_4 unithd 2300 16320 N DO 30 BY 1 STEP 460 0 ;
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ROW ROW_5 unithd 2300 19040 FS DO 30 BY 1 STEP 460 0 ;
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TRACKS X 230 DO 37 STEP 460 LAYER li1 ;
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TRACKS Y 170 DO 82 STEP 340 LAYER li1 ;
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TRACKS X 170 DO 50 STEP 340 LAYER met1 ;
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TRACKS Y 170 DO 82 STEP 340 LAYER met1 ;
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TRACKS X 230 DO 37 STEP 460 LAYER met2 ;
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TRACKS Y 230 DO 61 STEP 460 LAYER met2 ;
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TRACKS X 340 DO 25 STEP 680 LAYER met3 ;
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TRACKS Y 340 DO 41 STEP 680 LAYER met3 ;
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TRACKS X 460 DO 18 STEP 920 LAYER met4 ;
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TRACKS Y 460 DO 30 STEP 920 LAYER met4 ;
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TRACKS X 1700 DO 5 STEP 3400 LAYER met5 ;
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TRACKS Y 1700 DO 8 STEP 3400 LAYER met5 ;
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GCELLGRID X 0 DO 2 STEP 6900 ;
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GCELLGRID Y 0 DO 4 STEP 6900 ;
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VIAS 2 ;
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- via2_3_1400_480_1_4_320_320 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 85 165 145 85 + ROWCOL 1 4 ;
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- via3_4_1400_1400_3_3_400_400 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 200 85 65 200 + ROWCOL 3 3 ;
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END VIAS
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COMPONENTS 56 ;
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- FILLER_0_15 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9200 5440 ) N ;
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- FILLER_0_18 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 10580 5440 ) N ;
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- FILLER_0_23 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 12880 5440 ) N ;
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- FILLER_0_3 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 3680 5440 ) N ;
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- FILLER_0_8 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 5980 5440 ) N ;
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- FILLER_1_13 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 8280 8160 ) FS ;
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- FILLER_1_17 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 10120 8160 ) FS ;
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- FILLER_1_24 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 13340 8160 ) FS ;
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- FILLER_1_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 3680 8160 ) FS ;
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- FILLER_1_9 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 6440 8160 ) FS ;
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- FILLER_2_18 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 10580 10880 ) N ;
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- FILLER_2_26 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 14260 10880 ) N ;
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- FILLER_2_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 3680 10880 ) N ;
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- FILLER_2_9 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 6440 10880 ) N ;
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- FILLER_3_16 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 9660 13600 ) FS ;
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- FILLER_3_24 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 13340 13600 ) FS ;
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- FILLER_3_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 3680 13600 ) FS ;
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- FILLER_3_9 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 6440 13600 ) FS ;
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- FILLER_4_14 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 8740 16320 ) N ;
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- FILLER_4_18 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 10580 16320 ) N ;
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- FILLER_4_23 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 12880 16320 ) N ;
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- FILLER_4_3 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 3680 16320 ) N ;
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- FILLER_5_15 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9200 19040 ) FS ;
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- FILLER_5_18 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 10580 19040 ) FS ;
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- FILLER_5_26 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 14260 19040 ) FS ;
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- FILLER_5_3 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 3680 19040 ) FS ;
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- FILLER_5_8 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 5980 19040 ) FS ;
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- PHY_0 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 2300 5440 ) N ;
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- PHY_1 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 14720 5440 ) FN ;
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- PHY_10 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 2300 19040 ) FS ;
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- PHY_11 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 14720 19040 ) S ;
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- PHY_2 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 2300 8160 ) FS ;
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- PHY_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 14720 8160 ) S ;
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- PHY_4 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 2300 10880 ) N ;
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- PHY_5 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 14720 10880 ) FN ;
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- PHY_6 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 2300 13600 ) FS ;
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- PHY_7 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 14720 13600 ) S ;
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- PHY_8 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 2300 16320 ) N ;
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- PHY_9 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 14720 16320 ) FN ;
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- TAP_12 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 10120 5440 ) N ;
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- TAP_13 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 10120 10880 ) N ;
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- TAP_14 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 10120 16320 ) N ;
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- TAP_15 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 10120 19040 ) FS ;
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- gpio_default_value\[0\] sky130_fd_sc_hd__conb_1 + PLACED ( 7360 16320 ) FN ;
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- gpio_default_value\[10\] sky130_fd_sc_hd__conb_1 + PLACED ( 5060 13600 ) FS ;
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- gpio_default_value\[11\] sky130_fd_sc_hd__conb_1 + PLACED ( 11960 8160 ) S ;
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- gpio_default_value\[12\] sky130_fd_sc_hd__conb_1 + PLACED ( 8740 8160 ) S ;
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- gpio_default_value\[1\] sky130_fd_sc_hd__conb_1 + PLACED ( 11500 16320 ) N ;
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- gpio_default_value\[2\] sky130_fd_sc_hd__conb_1 + PLACED ( 4600 5440 ) FN ;
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- gpio_default_value\[3\] sky130_fd_sc_hd__conb_1 + PLACED ( 7820 5440 ) FN ;
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- gpio_default_value\[4\] sky130_fd_sc_hd__conb_1 + PLACED ( 11500 5440 ) FN ;
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- gpio_default_value\[5\] sky130_fd_sc_hd__conb_1 + PLACED ( 5060 8160 ) S ;
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- gpio_default_value\[6\] sky130_fd_sc_hd__conb_1 + PLACED ( 5060 10880 ) FN ;
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- gpio_default_value\[7\] sky130_fd_sc_hd__conb_1 + PLACED ( 8280 13600 ) S ;
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- gpio_default_value\[8\] sky130_fd_sc_hd__conb_1 + PLACED ( 7820 19040 ) S ;
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- gpio_default_value\[9\] sky130_fd_sc_hd__conb_1 + PLACED ( 4600 19040 ) S ;
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END COMPONENTS
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PINS 15 ;
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- VGND + NET VGND + SPECIAL + DIRECTION INOUT + USE GROUND
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+ PORT
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+ LAYER met3 ( -7140 -700 ) ( 7140 700 )
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+ LAYER met2 ( 4200 -11840 ) ( 5600 4960 )
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+ FIXED ( 9200 17040 ) N ;
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- VPWR + NET VPWR + SPECIAL + DIRECTION INOUT + USE POWER
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+ PORT
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+ LAYER met3 ( -7140 -700 ) ( 7140 700 )
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+ LAYER met2 ( -5200 -4440 ) ( -3800 12360 )
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+ FIXED ( 9200 9640 ) N ;
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- gpio_defaults[0] + NET gpio_defaults_low\[0\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -3000 ) ( 140 3000 )
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+ PLACED ( 3910 28000 ) N ;
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- gpio_defaults[10] + NET gpio_defaults_high\[10\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -3000 -300 ) ( 3000 300 )
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+ PLACED ( 0 21420 ) N ;
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- gpio_defaults[11] + NET gpio_defaults_low\[11\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -3000 ) ( 140 3000 )
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+ PLACED ( 3910 0 ) N ;
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- gpio_defaults[12] + NET gpio_defaults_low\[12\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -3000 ) ( 140 3000 )
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+ PLACED ( 5750 0 ) N ;
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- gpio_defaults[1] + NET gpio_defaults_high\[1\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met2 ( -140 -3000 ) ( 140 3000 )
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+ PLACED ( 5750 28000 ) N ;
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- gpio_defaults[2] + NET gpio_defaults_low\[2\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -3000 -300 ) ( 3000 300 )
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+ PLACED ( 0 5100 ) N ;
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- gpio_defaults[3] + NET gpio_defaults_low\[3\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -3000 -300 ) ( 3000 300 )
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+ PLACED ( 0 6460 ) N ;
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- gpio_defaults[4] + NET gpio_defaults_low\[4\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -3000 -300 ) ( 3000 300 )
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+ PLACED ( 0 7820 ) N ;
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- gpio_defaults[5] + NET gpio_defaults_low\[5\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -3000 -300 ) ( 3000 300 )
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+ PLACED ( 0 11900 ) N ;
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- gpio_defaults[6] + NET gpio_defaults_low\[6\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -3000 -300 ) ( 3000 300 )
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+ PLACED ( 0 13260 ) N ;
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- gpio_defaults[7] + NET gpio_defaults_low\[7\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -3000 -300 ) ( 3000 300 )
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+ PLACED ( 0 14620 ) N ;
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- gpio_defaults[8] + NET gpio_defaults_low\[8\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -3000 -300 ) ( 3000 300 )
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+ PLACED ( 0 18700 ) N ;
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- gpio_defaults[9] + NET gpio_defaults_low\[9\] + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -3000 -300 ) ( 3000 300 )
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+ PLACED ( 0 20060 ) N ;
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END PINS
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SPECIALNETS 2 ;
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- VGND ( PIN VGND ) ( * VNB ) ( * VGND ) + USE GROUND
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+ ROUTED met1 480 + SHAPE FOLLOWPIN ( 2300 21760 ) ( 16100 21760 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 2300 16320 ) ( 16100 16320 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 2300 10880 ) ( 16100 10880 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 2300 5440 ) ( 16100 5440 )
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NEW met3 1400 + SHAPE STRIPE ( 2060 17040 ) ( 16340 17040 )
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NEW met2 1400 + SHAPE STRIPE ( 14100 5200 ) ( 14100 22000 )
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NEW met2 0 + SHAPE STRIPE ( 14100 17040 ) via3_4_1400_1400_3_3_400_400
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NEW met1 0 + SHAPE STRIPE ( 14100 21760 ) via2_3_1400_480_1_4_320_320
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NEW met1 0 + SHAPE STRIPE ( 14100 16320 ) via2_3_1400_480_1_4_320_320
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NEW met1 0 + SHAPE STRIPE ( 14100 10880 ) via2_3_1400_480_1_4_320_320
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NEW met1 0 + SHAPE STRIPE ( 14100 5440 ) via2_3_1400_480_1_4_320_320 ;
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- VPWR ( PIN VPWR ) ( * VPB ) ( * VPWR ) + USE POWER
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+ ROUTED met1 480 + SHAPE FOLLOWPIN ( 2300 19040 ) ( 16100 19040 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 2300 13600 ) ( 16100 13600 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 2300 8160 ) ( 16100 8160 )
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NEW met3 1400 + SHAPE STRIPE ( 2060 9640 ) ( 16340 9640 )
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NEW met2 1400 + SHAPE STRIPE ( 4700 5200 ) ( 4700 22000 )
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NEW met2 0 + SHAPE STRIPE ( 4700 9640 ) via3_4_1400_1400_3_3_400_400
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NEW met1 0 + SHAPE STRIPE ( 4700 19040 ) via2_3_1400_480_1_4_320_320
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NEW met1 0 + SHAPE STRIPE ( 4700 13600 ) via2_3_1400_480_1_4_320_320
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NEW met1 0 + SHAPE STRIPE ( 4700 8160 ) via2_3_1400_480_1_4_320_320 ;
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END SPECIALNETS
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NETS 26 ;
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- gpio_defaults_high\[0\] ( gpio_default_value\[0\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[10\] ( PIN gpio_defaults[10] ) ( gpio_default_value\[10\] HI ) + USE SIGNAL
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+ ROUTED met1 ( 3450 15810 ) ( 5290 * )
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NEW met2 ( 3450 15810 ) ( * 22100 )
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NEW met3 ( 3450 22100 ) ( 4140 * )
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NEW met3 ( 4140 21420 ) ( * 22100 )
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NEW met3 ( 2300 21420 0 ) ( 4140 * )
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NEW li1 ( 5290 15810 ) L1M1_PR_MR
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NEW met1 ( 3450 15810 ) M1M2_PR
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NEW met2 ( 3450 22100 ) M2M3_PR ;
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- gpio_defaults_high\[11\] ( gpio_default_value\[11\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[12\] ( gpio_default_value\[12\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[1\] ( PIN gpio_defaults[1] ) ( gpio_default_value\[1\] HI ) + USE SIGNAL
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+ ROUTED met1 ( 7590 17850 ) ( 11730 * )
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NEW met2 ( 7590 17850 ) ( * 19380 )
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NEW met2 ( 7130 19380 ) ( 7590 * )
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NEW met2 ( 7130 19380 ) ( * 23460 )
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NEW met2 ( 6670 23460 ) ( 7130 * )
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NEW met2 ( 6670 23460 ) ( * 25500 )
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NEW met2 ( 5750 25500 0 ) ( 6670 * )
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NEW li1 ( 11730 17850 ) L1M1_PR_MR
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NEW met1 ( 7590 17850 ) M1M2_PR ;
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- gpio_defaults_high\[2\] ( gpio_default_value\[2\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[3\] ( gpio_default_value\[3\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[4\] ( gpio_default_value\[4\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[5\] ( gpio_default_value\[5\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[6\] ( gpio_default_value\[6\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[7\] ( gpio_default_value\[7\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[8\] ( gpio_default_value\[8\] HI ) + USE SIGNAL ;
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- gpio_defaults_high\[9\] ( gpio_default_value\[9\] HI ) + USE SIGNAL ;
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- gpio_defaults_low\[0\] ( PIN gpio_defaults[0] ) ( gpio_default_value\[0\] LO ) + USE SIGNAL
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+ ROUTED met1 ( 7130 18530 ) ( 7590 * )
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NEW met2 ( 7130 18530 ) ( * 18700 )
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NEW met2 ( 6670 18700 ) ( 7130 * )
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NEW met2 ( 6670 18700 ) ( * 22780 )
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NEW met2 ( 5290 22780 ) ( 6670 * )
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NEW met2 ( 5290 22780 ) ( * 25500 )
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NEW met2 ( 3910 25500 0 ) ( 5290 * )
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NEW li1 ( 7590 18530 ) L1M1_PR_MR
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NEW met1 ( 7130 18530 ) M1M2_PR ;
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- gpio_defaults_low\[10\] ( gpio_default_value\[10\] LO ) + USE SIGNAL ;
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- gpio_defaults_low\[11\] ( PIN gpio_defaults[11] ) ( gpio_default_value\[11\] LO ) + USE SIGNAL
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+ ROUTED met2 ( 2990 2380 ) ( 3910 * 0 )
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NEW met2 ( 2990 2380 ) ( * 9010 )
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NEW met1 ( 2990 9010 ) ( 12190 * )
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NEW met1 ( 2990 9010 ) M1M2_PR
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NEW li1 ( 12190 9010 ) L1M1_PR_MR ;
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- gpio_defaults_low\[12\] ( PIN gpio_defaults[12] ) ( gpio_default_value\[12\] LO ) + USE SIGNAL
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+ ROUTED met2 ( 5750 2380 0 ) ( 6670 * )
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NEW met2 ( 6670 2380 ) ( * 8670 )
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NEW met1 ( 6670 8670 ) ( 8970 * )
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NEW met1 ( 6670 8670 ) M1M2_PR
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NEW li1 ( 8970 8670 ) L1M1_PR_MR ;
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- gpio_defaults_low\[1\] ( gpio_default_value\[1\] LO ) + USE SIGNAL ;
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- gpio_defaults_low\[2\] ( PIN gpio_defaults[2] ) ( gpio_default_value\[2\] LO ) + USE SIGNAL
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+ ROUTED met3 ( 2300 5100 0 ) ( 4140 * )
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NEW met3 ( 4140 5100 ) ( * 5780 )
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NEW met3 ( 3450 5780 ) ( 4140 * )
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NEW met2 ( 3450 5780 ) ( * 6970 )
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NEW met1 ( 3450 6970 ) ( 4830 * )
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NEW met2 ( 3450 5780 ) M2M3_PR
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NEW met1 ( 3450 6970 ) M1M2_PR
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NEW li1 ( 4830 6970 ) L1M1_PR_MR ;
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- gpio_defaults_low\[3\] ( PIN gpio_defaults[3] ) ( gpio_default_value\[3\] LO ) + USE SIGNAL
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+ ROUTED met3 ( 2300 6460 0 ) ( 5750 * )
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NEW met2 ( 5750 6460 ) ( * 6630 )
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NEW met1 ( 5750 6630 ) ( 8050 * )
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NEW met2 ( 5750 6460 ) M2M3_PR
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NEW met1 ( 5750 6630 ) M1M2_PR
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NEW li1 ( 8050 6630 ) L1M1_PR_MR ;
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- gpio_defaults_low\[4\] ( PIN gpio_defaults[4] ) ( gpio_default_value\[4\] LO ) + USE SIGNAL
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+ ROUTED met1 ( 6210 7650 ) ( 11730 * )
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NEW met2 ( 6210 7650 ) ( * 7820 )
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NEW met3 ( 2300 7820 0 ) ( 6210 * )
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NEW li1 ( 11730 7650 ) L1M1_PR_MR
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NEW met1 ( 6210 7650 ) M1M2_PR
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NEW met2 ( 6210 7820 ) M2M3_PR ;
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- gpio_defaults_low\[5\] ( PIN gpio_defaults[5] ) ( gpio_default_value\[5\] LO ) + USE SIGNAL
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+ ROUTED met1 ( 5290 9690 ) ( 5750 * )
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NEW met2 ( 5750 9690 ) ( * 11900 )
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NEW met3 ( 2300 11900 0 ) ( 5750 * )
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NEW li1 ( 5290 9690 ) L1M1_PR_MR
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NEW met1 ( 5750 9690 ) M1M2_PR
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NEW met2 ( 5750 11900 ) M2M3_PR ;
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- gpio_defaults_low\[6\] ( PIN gpio_defaults[6] ) ( gpio_default_value\[6\] LO ) + USE SIGNAL
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+ ROUTED met1 ( 5290 13090 ) ( 5750 * )
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NEW met2 ( 5750 13090 ) ( * 13260 )
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NEW met3 ( 2300 13260 0 ) ( 5750 * )
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NEW li1 ( 5290 13090 ) L1M1_PR_MR
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NEW met1 ( 5750 13090 ) M1M2_PR
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NEW met2 ( 5750 13260 ) M2M3_PR ;
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- gpio_defaults_low\[7\] ( PIN gpio_defaults[7] ) ( gpio_default_value\[7\] LO ) + USE SIGNAL
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+ ROUTED met3 ( 2300 14620 0 ) ( 5750 * )
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NEW met2 ( 5750 14450 ) ( * 14620 )
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NEW met1 ( 5750 14450 ) ( 8510 * )
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NEW met2 ( 5750 14620 ) M2M3_PR
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NEW met1 ( 5750 14450 ) M1M2_PR
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NEW li1 ( 8510 14450 ) L1M1_PR_MR ;
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- gpio_defaults_low\[8\] ( PIN gpio_defaults[8] ) ( gpio_default_value\[8\] LO ) + USE SIGNAL
|
|
+ ROUTED met3 ( 2300 18700 0 ) ( 6210 * )
|
|
NEW met2 ( 6210 18700 ) ( * 19550 )
|
|
NEW met1 ( 6210 19550 ) ( 8050 * )
|
|
NEW met2 ( 6210 18700 ) M2M3_PR
|
|
NEW met1 ( 6210 19550 ) M1M2_PR
|
|
NEW li1 ( 8050 19550 ) L1M1_PR_MR ;
|
|
- gpio_defaults_low\[9\] ( PIN gpio_defaults[9] ) ( gpio_default_value\[9\] LO ) + USE SIGNAL
|
|
+ ROUTED met3 ( 2300 20060 0 ) ( 5750 * )
|
|
NEW met2 ( 5750 19890 ) ( * 20060 )
|
|
NEW met1 ( 4830 19890 ) ( 5750 * )
|
|
NEW met2 ( 5750 20060 ) M2M3_PR
|
|
NEW met1 ( 5750 19890 ) M1M2_PR
|
|
NEW li1 ( 4830 19890 ) L1M1_PR_MR ;
|
|
END NETS
|
|
END DESIGN
|