mirror of https://github.com/efabless/caravel.git
58 lines
1.6 KiB
Verilog
58 lines
1.6 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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// This module represents an unprogrammed mask revision
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// block that is configured with via programming on the
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// chip top level. This value is passed to the block as
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// a parameter
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module user_id_programming #(
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parameter USER_PROJECT_ID = 32'h0
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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output [31:0] mask_rev
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);
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wire [31:0] mask_rev;
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wire [31:0] user_proj_id_high;
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wire [31:0] user_proj_id_low;
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// For the mask revision input, use an array of digital constant logic cells
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sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
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`ifdef USE_POWER_PINS
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.VPWR(VPWR),
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.VPB(VPWR),
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.VNB(VGND),
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.VGND(VGND),
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`endif
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.HI(user_proj_id_high),
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.LO(user_proj_id_low)
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);
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genvar i;
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generate
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for (i = 0; i < 32; i = i+1) begin
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assign mask_rev[i] = (USER_PROJECT_ID & (32'h01 << i)) ?
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user_proj_id_high[i] : user_proj_id_low[i];
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end
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endgenerate
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endmodule
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`default_nettype wire
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