mirror of https://github.com/efabless/caravel.git
139 lines
4.7 KiB
Verilog
139 lines
4.7 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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// `default_nettype none
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/* Define the array of GPIO pads. Note that the analog project support
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* version of caravel (caravan) defines fewer GPIO and replaces them
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* with analog in the chip_io_alt module. Because the pad signalling
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* remains the same, `MPRJ_IO_PADS does not change, so a local parameter
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* is made that can be made smaller than `MPRJ_IO_PADS to accommodate
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* the analog pads.
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*/
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module mprj_io #(
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parameter AREA1PADS = `MPRJ_IO_PADS_1,
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parameter TOTAL_PADS = `MPRJ_IO_PADS
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) (
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inout vddio,
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inout vssio,
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inout vdda,
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inout vssa,
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inout vccd,
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inout vssd,
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inout vdda1,
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inout vdda2,
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inout vssa1,
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inout vssa2,
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inout vccd1,
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inout vccd2,
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inout vssd1,
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inout vssd2,
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input vddio_q,
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input vssio_q,
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input analog_a,
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input analog_b,
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input porb_h,
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inout [TOTAL_PADS-1:0] io,
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input [TOTAL_PADS-1:0] io_out,
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input [TOTAL_PADS-1:0] oeb,
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input [TOTAL_PADS-1:0] hldh_n,
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input [TOTAL_PADS-1:0] enh,
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input [TOTAL_PADS-1:0] inp_dis,
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input [TOTAL_PADS-1:0] ib_mode_sel,
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input [TOTAL_PADS-1:0] vtrip_sel,
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input [TOTAL_PADS-1:0] slow_sel,
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input [TOTAL_PADS-1:0] holdover,
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input [TOTAL_PADS-1:0] analog_en,
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input [TOTAL_PADS-1:0] analog_sel,
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input [TOTAL_PADS-1:0] analog_pol,
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input [TOTAL_PADS*3-1:0] dm,
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output [TOTAL_PADS-1:0] io_in,
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output [TOTAL_PADS-1:0] io_in_3v3,
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inout [TOTAL_PADS-10:0] analog_io,
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inout [TOTAL_PADS-10:0] analog_noesd_io
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);
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wire [TOTAL_PADS-1:0] loop1_io;
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wire [6:0] no_connect_1a, no_connect_1b;
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wire [1:0] no_connect_2a, no_connect_2b;
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sky130_ef_io__gpiov2_pad_wrapped area1_io_pad [AREA1PADS - 1:0] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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,.PAD(io[AREA1PADS - 1:0]),
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`endif
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.OUT(io_out[AREA1PADS - 1:0]),
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.OE_N(oeb[AREA1PADS - 1:0]),
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.HLD_H_N(hldh_n[AREA1PADS - 1:0]),
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.ENABLE_H(enh[AREA1PADS - 1:0]),
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.ENABLE_INP_H(loop1_io[AREA1PADS - 1:0]),
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.ENABLE_VDDA_H(porb_h),
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.ENABLE_VSWITCH_H(vssio),
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.ENABLE_VDDIO(vccd),
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.INP_DIS(inp_dis[AREA1PADS - 1:0]),
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.IB_MODE_SEL(ib_mode_sel[AREA1PADS - 1:0]),
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.VTRIP_SEL(vtrip_sel[AREA1PADS - 1:0]),
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.SLOW(slow_sel[AREA1PADS - 1:0]),
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.HLD_OVR(holdover[AREA1PADS - 1:0]),
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.ANALOG_EN(analog_en[AREA1PADS - 1:0]),
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.ANALOG_SEL(analog_sel[AREA1PADS - 1:0]),
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.ANALOG_POL(analog_pol[AREA1PADS - 1:0]),
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.DM(dm[AREA1PADS*3 - 1:0]),
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.PAD_A_NOESD_H({analog_noesd_io[AREA1PADS - 8:0], no_connect_1a}),
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.PAD_A_ESD_0_H({analog_io[AREA1PADS - 8:0], no_connect_1b}),
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.PAD_A_ESD_1_H(),
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.IN(io_in[AREA1PADS - 1:0]),
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.IN_H(io_in_3v3[AREA1PADS - 1:0]),
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.TIE_HI_ESD(),
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.TIE_LO_ESD(loop1_io[AREA1PADS - 1:0])
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);
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sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [TOTAL_PADS - AREA1PADS - 1:0] (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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,.PAD(io[TOTAL_PADS - 1:AREA1PADS]),
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`endif
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.OUT(io_out[TOTAL_PADS - 1:AREA1PADS]),
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.OE_N(oeb[TOTAL_PADS - 1:AREA1PADS]),
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.HLD_H_N(hldh_n[TOTAL_PADS - 1:AREA1PADS]),
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.ENABLE_H(enh[TOTAL_PADS - 1:AREA1PADS]),
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.ENABLE_INP_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
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.ENABLE_VDDA_H(porb_h),
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.ENABLE_VSWITCH_H(vssio),
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.ENABLE_VDDIO(vccd),
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.INP_DIS(inp_dis[TOTAL_PADS - 1:AREA1PADS]),
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.IB_MODE_SEL(ib_mode_sel[TOTAL_PADS - 1:AREA1PADS]),
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.VTRIP_SEL(vtrip_sel[TOTAL_PADS - 1:AREA1PADS]),
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.SLOW(slow_sel[TOTAL_PADS - 1:AREA1PADS]),
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.HLD_OVR(holdover[TOTAL_PADS - 1:AREA1PADS]),
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.ANALOG_EN(analog_en[TOTAL_PADS - 1:AREA1PADS]),
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.ANALOG_SEL(analog_sel[TOTAL_PADS - 1:AREA1PADS]),
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.ANALOG_POL(analog_pol[TOTAL_PADS - 1:AREA1PADS]),
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.DM(dm[TOTAL_PADS*3 - 1:AREA1PADS*3]),
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.PAD_A_NOESD_H({no_connect_2a, analog_noesd_io[TOTAL_PADS - 10:AREA1PADS - 7]}),
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.PAD_A_ESD_0_H({no_connect_2b, analog_io[TOTAL_PADS - 10:AREA1PADS - 7]}),
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.PAD_A_ESD_1_H(),
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.IN(io_in[TOTAL_PADS - 1:AREA1PADS]),
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.IN_H(io_in_3v3[TOTAL_PADS - 1:AREA1PADS]),
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.TIE_HI_ESD(),
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.TIE_LO_ESD(loop1_io[TOTAL_PADS - 1:AREA1PADS])
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);
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endmodule
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// `default_nettype wire
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