mirror of https://github.com/efabless/caravel.git
72 lines
2.1 KiB
Verilog
72 lines
2.1 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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// Digital PLL (ring oscillator + controller)
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// Technically this is a frequency locked loop, not a phase locked loop.
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`include "digital_pll_controller.v"
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`include "ring_osc2x13.v"
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module digital_pll(
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`ifdef USE_POWER_PINS
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VPWR,
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VGND,
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`endif
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resetb, enable, osc, clockp, div, dco, ext_trim);
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`ifdef USE_POWER_PINS
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input VPWR;
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input VGND;
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`endif
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input resetb; // Sense negative reset
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input enable; // Enable PLL
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input osc; // Input oscillator to match
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input [4:0] div; // PLL feedback division ratio
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input dco; // Run in DCO mode
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input [25:0] ext_trim; // External trim for DCO mode
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output [1:0] clockp; // Two 90 degree clock phases
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wire [25:0] itrim; // Internally generated trim bits
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wire [25:0] otrim; // Trim bits applied to the ring oscillator
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wire creset; // Controller reset
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wire ireset; // Internal reset (external reset OR disable)
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assign ireset = ~resetb | ~enable;
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// In DCO mode: Hold controller in reset and apply external trim value
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assign itrim = (dco == 1'b0) ? otrim : ext_trim;
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assign creset = (dco == 1'b0) ? ireset : 1'b1;
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ring_osc2x13 ringosc (
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.reset(ireset),
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.trim(itrim),
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.clockp(clockp)
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);
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digital_pll_controller pll_control (
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.reset(creset),
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.clock(clockp[0]),
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.osc(osc),
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.div(div),
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.trim(otrim)
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);
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endmodule
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`default_nettype wire
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