mirror of https://github.com/efabless/caravel.git
112 lines
3.3 KiB
Verilog
112 lines
3.3 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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// This routine synchronizes the
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module caravel_clocking(
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`ifdef USE_POWER_PINS
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input vdd1v8,
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input vss,
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`endif
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input resetb, // Master (negative sense) reset
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input ext_clk_sel, // 0=use PLL clock, 1=use external (pad) clock
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input ext_clk, // External pad (slow) clock
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input pll_clk, // Internal PLL (fast) clock
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input pll_clk90, // Internal PLL (fast) clock, 90 degree phase
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input [2:0] sel, // Select clock divider value (0=thru, 1=divide-by-2, etc.)
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input [2:0] sel2, // Select clock divider value for 90 degree phase divided clock
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input ext_reset, // Positive sense reset from housekeeping SPI.
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output core_clk, // Output core clock
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output user_clk, // Output user (secondary) clock
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output resetb_sync // Output propagated and buffered reset
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);
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wire pll_clk_sel;
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wire pll_clk_divided;
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wire pll_clk90_divided;
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wire core_ext_clk;
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reg use_pll_first;
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reg use_pll_second;
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reg ext_clk_syncd_pre;
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reg ext_clk_syncd;
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assign pll_clk_sel = ~ext_clk_sel;
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// Note that this implementation does not guard against switching to
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// the PLL clock if the PLL clock is not present.
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always @(posedge pll_clk or negedge resetb) begin
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if (resetb == 1'b0) begin
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use_pll_first <= 1'b0;
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use_pll_second <= 1'b0;
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ext_clk_syncd <= 1'b0;
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end else begin
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use_pll_first <= pll_clk_sel;
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use_pll_second <= use_pll_first;
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ext_clk_syncd_pre <= ext_clk; // Sync ext_clk to pll_clk
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ext_clk_syncd <= ext_clk_syncd_pre; // Do this twice (resolve metastability)
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end
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end
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// Apply PLL clock divider
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clock_div #(
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.SIZE(3)
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) divider (
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.in(pll_clk),
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.out(pll_clk_divided),
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.N(sel),
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.resetb(resetb)
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);
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// Secondary PLL clock divider for user space access
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clock_div #(
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.SIZE(3)
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) divider2 (
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.in(pll_clk90),
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.out(pll_clk90_divided),
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.N(sel2),
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.resetb(resetb)
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);
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// Multiplex the clock output
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assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
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assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
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assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk;
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// Reset assignment. "reset" comes from POR, while "ext_reset"
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// comes from standalone SPI (and is normally zero unless
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// activated from the SPI).
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// Staged-delay reset
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reg [2:0] reset_delay;
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always @(posedge core_clk or negedge resetb) begin
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if (resetb == 1'b0) begin
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reset_delay <= 3'b111;
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end else begin
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reset_delay <= {1'b0, reset_delay[2:1]};
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end
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end
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assign resetb_sync = ~(reset_delay[0] | ext_reset);
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endmodule
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`default_nettype wire
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