mirror of https://github.com/efabless/caravel.git
380 lines
11 KiB
Systemverilog
380 lines
11 KiB
Systemverilog
`timescale 1 ns / 1 ps
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`ifdef VCS
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`ifndef GL
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`include "includes.v" // in case of RTL coverage is needed and it doesn't work correctly without include files by this way
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`endif // ~ GL
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`ifndef ENABLE_SDF
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`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
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`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
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`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
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`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
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`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
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`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
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`else
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`include "cvc-pdk/sky130_ef_io.v"
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`include "cvc-pdk/sky130_fd_io.v"
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`include "cvc-pdk/primitives_hd.v"
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`include "cvc-pdk/sky130_fd_sc_hd.v"
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`include "cvc-pdk/primitives_hvl.v"
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`include "cvc-pdk/sky130_fd_sc_hvl.v"
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`endif // ~ ENABLE_SDF
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`endif // VCS
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module caravel_top ;
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// parameter FILENAME = {"hex_files/",`TESTNAME,".hex"};
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parameter FILENAME={"hex_files/",`TESTNAME,".hex"};
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initial begin
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`ifdef VCS
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`ifdef ENABLE_SDF
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$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME , `CORNER,"-",`SDF_POSTFIX, ".vpd"});
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`else
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$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME ,".vpd"});
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`endif
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$vcdpluson();
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`else
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$dumpfile ({"sim/",`TAG,"/",`SIM,"-",`TESTNAME,"/",`SIM,"-",`TESTNAME,".vcd"});
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$dumpvars (0, caravel_top);
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`endif
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end
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`ifdef VCS
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`ifdef ENABLE_SDF
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`include "sdf_includes.v"
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`endif
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`endif // VCS
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wire vddio_tb; // Common 3.3V padframe/ESD power
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wire vddio_2_tb; // Common 3.3V padframe/ESD power
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wire vssio_tb; // Common padframe/ESD ground
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wire vssio_2_tb; // Common padframe/ESD ground
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wire vdda_tb; // Management 3.3V power
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wire vssa_tb; // Common analog ground
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wire vccd_tb; // Management/Common 1.8V power
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wire vssd_tb; // Common digital ground
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wire vdda1_tb; // User area 1 3.3V power
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wire vdda1_2_tb; // User area 1 3.3V power
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wire vdda2_tb; // User area 2 3.3V power
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wire vssa1_tb; // User area 1 analog ground
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wire vssa1_2_tb; // User area 1 analog ground
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wire vssa2_tb; // User area 2 analog ground
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wire vccd1_tb; // User area 1 1.8V power
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wire vccd2_tb; // User area 2 1.8V power
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wire vssd1_tb; // User area 1 digital ground
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wire vssd2_tb; // User area 2 digital ground
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wire gpio_tb; // Used for external LDO control
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wire [38-1:0] mprj_io_tb;
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reg clock_tb; // CMOS core clock input; not a crystal
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wire resetb_tb; // Reset input (sense inverted)
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// Note that only two flash data pins are dedicated to the
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// management SoC wrapper. The management SoC exports the
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// quad SPI mode status to make use of the top two mprj_io
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// pins for io2 and io3.
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wire flash_csb_tb;
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wire flash_clk_tb;
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wire flash_io0_tb;
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wire flash_io1_tb;
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`ifdef CARAVAN
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caravan uut (
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`else
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caravel uut (
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`endif
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.vddio (vddio_tb),
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.vddio_2 (vddio_2_tb),
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.vssio (vssio_tb),
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.vssio_2 (vssio_2_tb),
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.vdda (vdda_tb),
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.vssa (vssa_tb),
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.vccd (vccd_tb),
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.vssd (vssd_tb),
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.vdda1 (vdda1_tb),
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.vdda1_2 (vdda1_2_tb),
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.vdda2 (vdda2_tb),
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.vssa1 (vssa1_tb),
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.vssa1_2 (vssa1_2_tb),
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.vssa2 (vssa2_tb),
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.vccd1 (vccd1_tb),
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.vccd2 (vccd2_tb),
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.vssd1 (vssd1_tb),
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.vssd2 (vssd2_tb),
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.clock (clock_tb),
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.gpio (gpio_tb),
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.mprj_io (mprj_io_tb),
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.flash_csb(flash_csb_tb),
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.flash_clk(flash_clk_tb),
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.flash_io0(flash_io0_tb),
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.flash_io1(flash_io1_tb),
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.resetb (resetb_tb)
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);
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spiflash #(
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FILENAME
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) spiflash (
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.csb(flash_csb_tb),
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.clk(flash_clk_tb),
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.io0(flash_io0_tb),
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.io1(flash_io1_tb),
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.io2(), // not used
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.io3() // not used
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);
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mac macros();
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// make speical variables for the mprj input to assign the input without writing to the output gpios
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// cocotb limitation #2587: iverilog deal with array as 1 object not multiple of objects so can't write to only 1 element
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wire bin0;
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wire bin0_en;
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wire bin1;
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wire bin1_en;
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wire bin2;
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wire bin2_en;
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wire bin3;
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wire bin3_en;
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wire bin4;
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wire bin4_en;
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wire bin5;
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wire bin5_en;
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wire bin6;
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wire bin6_en;
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wire bin7;
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wire bin7_en;
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wire bin8;
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wire bin8_en;
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wire bin9;
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wire bin9_en;
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wire bin10;
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wire bin10_en;
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wire bin11;
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wire bin11_en;
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wire bin12;
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wire bin12_en;
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wire bin13;
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wire bin13_en;
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wire bin14;
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wire bin14_en;
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wire bin15;
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wire bin15_en;
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wire bin16;
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wire bin16_en;
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wire bin17;
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wire bin17_en;
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wire bin18;
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wire bin18_en;
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wire bin19;
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wire bin19_en;
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wire bin20;
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wire bin20_en;
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wire bin21;
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wire bin21_en;
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wire bin22;
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wire bin22_en;
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wire bin23;
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wire bin23_en;
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wire bin24;
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wire bin24_en;
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wire bin25;
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wire bin25_en;
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wire bin26;
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wire bin26_en;
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wire bin27;
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wire bin27_en;
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wire bin28;
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wire bin28_en;
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wire bin29;
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wire bin29_en;
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wire bin30;
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wire bin30_en;
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wire bin31;
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wire bin31_en;
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wire bin32;
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wire bin32_en;
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wire bin33;
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wire bin33_en;
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wire bin34;
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wire bin34_en;
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wire bin35;
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wire bin35_en;
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wire bin36;
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wire bin36_en;
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wire bin37;
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wire bin37_en;
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assign mprj_io_tb[0] = (bin0_en) ? bin0 : 1'bz;
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assign mprj_io_tb[1] = (bin1_en) ? bin1 : 1'bz;
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assign mprj_io_tb[2] = (bin2_en) ? bin2 : 1'bz;
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assign mprj_io_tb[3] = (bin3_en) ? bin3 : 1'bz;
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assign mprj_io_tb[4] = (bin4_en) ? bin4 : 1'bz;
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assign mprj_io_tb[5] = (bin5_en) ? bin5 : 1'bz;
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assign mprj_io_tb[6] = (bin6_en) ? bin6 : 1'bz;
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assign mprj_io_tb[7] = (bin7_en) ? bin7 : 1'bz;
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assign mprj_io_tb[8] = (bin8_en) ? bin8 : 1'bz;
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assign mprj_io_tb[9] = (bin9_en) ? bin9 : 1'bz;
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assign mprj_io_tb[10] = (bin10_en) ? bin10 : 1'bz;
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assign mprj_io_tb[11] = (bin11_en) ? bin11 : 1'bz;
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assign mprj_io_tb[12] = (bin12_en) ? bin12 : 1'bz;
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assign mprj_io_tb[13] = (bin13_en) ? bin13 : 1'bz;
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assign mprj_io_tb[14] = (bin14_en) ? bin14 : 1'bz;
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assign mprj_io_tb[15] = (bin15_en) ? bin15 : 1'bz;
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assign mprj_io_tb[16] = (bin16_en) ? bin16 : 1'bz;
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assign mprj_io_tb[17] = (bin17_en) ? bin17 : 1'bz;
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assign mprj_io_tb[18] = (bin18_en) ? bin18 : 1'bz;
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assign mprj_io_tb[19] = (bin19_en) ? bin19 : 1'bz;
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assign mprj_io_tb[20] = (bin20_en) ? bin20 : 1'bz;
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assign mprj_io_tb[21] = (bin21_en) ? bin21 : 1'bz;
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assign mprj_io_tb[22] = (bin22_en) ? bin22 : 1'bz;
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assign mprj_io_tb[23] = (bin23_en) ? bin23 : 1'bz;
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assign mprj_io_tb[24] = (bin24_en) ? bin24 : 1'bz;
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assign mprj_io_tb[25] = (bin25_en) ? bin25 : 1'bz;
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assign mprj_io_tb[26] = (bin26_en) ? bin26 : 1'bz;
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assign mprj_io_tb[27] = (bin27_en) ? bin27 : 1'bz;
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assign mprj_io_tb[28] = (bin28_en) ? bin28 : 1'bz;
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assign mprj_io_tb[29] = (bin29_en) ? bin29 : 1'bz;
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assign mprj_io_tb[30] = (bin30_en) ? bin30 : 1'bz;
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assign mprj_io_tb[31] = (bin31_en) ? bin31 : 1'bz;
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assign mprj_io_tb[32] = (bin32_en) ? bin32 : 1'bz;
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assign mprj_io_tb[33] = (bin33_en) ? bin33 : 1'bz;
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assign mprj_io_tb[34] = (bin34_en) ? bin34 : 1'bz;
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assign mprj_io_tb[35] = (bin35_en) ? bin35 : 1'bz;
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assign mprj_io_tb[36] = (bin36_en) ? bin36 : 1'bz;
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assign mprj_io_tb[37] = (bin37_en) ? bin37 : 1'bz;
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// to read from mprj array with iverilog
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wire bin0_monitor;
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wire bin1_monitor;
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wire bin2_monitor;
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wire bin3_monitor;
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wire bin4_monitor;
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wire bin5_monitor;
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wire bin6_monitor;
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wire bin7_monitor;
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wire bin8_monitor;
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wire bin9_monitor;
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wire bin10_monitor;
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wire bin11_monitor;
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wire bin12_monitor;
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wire bin13_monitor;
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wire bin14_monitor;
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wire bin15_monitor;
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wire bin16_monitor;
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wire bin17_monitor;
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wire bin18_monitor;
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wire bin19_monitor;
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wire bin20_monitor;
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wire bin21_monitor;
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wire bin22_monitor;
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wire bin23_monitor;
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wire bin24_monitor;
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wire bin25_monitor;
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wire bin26_monitor;
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wire bin27_monitor;
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wire bin28_monitor;
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wire bin29_monitor;
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wire bin30_monitor;
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wire bin31_monitor;
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wire bin32_monitor;
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wire bin33_monitor;
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wire bin34_monitor;
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wire bin35_monitor;
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wire bin36_monitor;
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wire bin37_monitor;
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assign bin0_monitor = mprj_io_tb[0];
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assign bin1_monitor = mprj_io_tb[1];
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assign bin2_monitor = mprj_io_tb[2];
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assign bin3_monitor = mprj_io_tb[3];
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assign bin4_monitor = mprj_io_tb[4];
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assign bin5_monitor = mprj_io_tb[5];
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assign bin6_monitor = mprj_io_tb[6];
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assign bin7_monitor = mprj_io_tb[7];
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assign bin8_monitor = mprj_io_tb[8];
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assign bin9_monitor = mprj_io_tb[9];
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assign bin10_monitor = mprj_io_tb[10];
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assign bin11_monitor = mprj_io_tb[11];
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assign bin12_monitor = mprj_io_tb[12];
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assign bin13_monitor = mprj_io_tb[13];
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assign bin14_monitor = mprj_io_tb[14];
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assign bin15_monitor = mprj_io_tb[15];
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assign bin16_monitor = mprj_io_tb[16];
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assign bin17_monitor = mprj_io_tb[17];
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assign bin18_monitor = mprj_io_tb[18];
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assign bin19_monitor = mprj_io_tb[19];
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assign bin20_monitor = mprj_io_tb[20];
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assign bin21_monitor = mprj_io_tb[21];
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assign bin22_monitor = mprj_io_tb[22];
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assign bin23_monitor = mprj_io_tb[23];
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assign bin24_monitor = mprj_io_tb[24];
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assign bin25_monitor = mprj_io_tb[25];
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assign bin26_monitor = mprj_io_tb[26];
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assign bin27_monitor = mprj_io_tb[27];
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assign bin28_monitor = mprj_io_tb[28];
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assign bin29_monitor = mprj_io_tb[29];
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assign bin30_monitor = mprj_io_tb[30];
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assign bin31_monitor = mprj_io_tb[31];
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assign bin32_monitor = mprj_io_tb[32];
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assign bin33_monitor = mprj_io_tb[33];
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assign bin34_monitor = mprj_io_tb[34];
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assign bin35_monitor = mprj_io_tb[35];
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assign bin36_monitor = mprj_io_tb[36];
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assign bin37_monitor = mprj_io_tb[37];
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endmodule
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// module that has all needed macros by cocotb
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module mac;
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reg [7:0] MPRJ_IO_PADS_1 = `ifdef MPRJ_IO_PADS_1 `MPRJ_IO_PADS_1 `else 0 `endif; /* number of user GPIO pads on user1 side */
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reg [7:0] MPRJ_IO_PADS_2 = `ifdef MPRJ_IO_PADS_2 `MPRJ_IO_PADS_2 `else 0 `endif; /* number of user GPIO pads on user2 side */
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reg [7:0] MPRJ_IO_PADS = `ifdef MPRJ_IO_PADS `MPRJ_IO_PADS `else 0 `endif;
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reg [7:0] MPRJ_PWR_PADS_1 =`ifdef MPRJ_PWR_PADS_1 `MPRJ_PWR_PADS_1 `else 0 `endif; /* vdda1, vccd1 enable/disable control */
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reg [7:0] MPRJ_PWR_PADS_2 = `ifdef MPRJ_PWR_PADS_2 `MPRJ_PWR_PADS_2 `else 0 `endif; /* vdda2, vccd2 enable/disable control */
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reg [7:0] MPRJ_PWR_PADS =`ifdef MPRJ_PWR_PADS `MPRJ_PWR_PADS `else 0 `endif;
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// Analog pads are only used by the "caravan" module and associated
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// modules such as user_analog_project_wrapper and chip_io_alt.
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reg [7:0] ANALOG_PADS_1 = `ifdef ANALOG_PADS_1 `ANALOG_PADS_1 `else 0 `endif;
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reg [7:0] ANALOG_PADS_2 = `ifdef ANALOG_PADS_2 `ANALOG_PADS_2 `else 0 `endif;
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reg [7:0] ANALOG_PADS = `ifdef ANALOG_PADS `ANALOG_PADS `else 0 `endif;
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// Type and size of soc_mem
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reg USE_CUSTOM_DFFRAM = `ifdef USE_CUSTOM_DFFRAM 1 `else 0 `endif;
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// don't change the following without double checking addr widths
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reg [7:0] MEM_WORDS = `ifdef MEM_WORDS `MEM_WORDS `else 0 `endif;
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// Number of columns in the custom memory; takes one of three values:
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// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
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reg [7:0] DFFRAM_WSIZE = `ifdef DFFRAM_WSIZE `DFFRAM_WSIZE `else 0 `endif;
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reg [7:0] DFFRAM_USE_LATCH = `ifdef DFFRAM_USE_LATCH `DFFRAM_USE_LATCH `else 0 `endif;
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// not really parameterized but just to easily keep track of the number
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// of ram_block across different modules
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reg [7:0] RAM_BLOCKS = `ifdef RAM_BLOCKS `RAM_BLOCKS `else 0 `endif;
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// Clock divisor default value
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reg [7:0] CLK_DIV = `ifdef CLK_DIV `CLK_DIV `else 0 `endif;
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// GPIO control default mode and enable for most I/Os
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// Most I/Os set to be user bidirectional pins on power-up.
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reg [7:0] MGMT_INIT = `ifdef MGMT_INIT `MGMT_INIT `else 0 `endif;
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reg [7:0] OENB_INIT = `ifdef OENB_INIT `OENB_INIT `else 0 `endif;
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reg [7:0] DM_INIT = `ifdef DM_INIT `DM_INIT `else 0 `endif;
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// GL
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reg GL = `ifdef GL 1 `else 0 `endif;
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reg CARAVAN = `ifdef CARAVAN 1 `else 0 `endif;
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endmodule |