caravel/signoff/caravel_clocking/openlane-signoff/wire_length.txt

core_clk 16.9
ext_clk 17.44
ext_clk_sel 9.405
ext_reset 9.065
pll_clk 83.92
pll_clk90 56.695
resetb 10.26
resetb_sync 28.755
sel2[0] 7.365
sel2[1] 7.83
sel2[2] 8.005
sel[0] 8.92
sel[1] 9.745
sel[2] 8.73
user_clk 22.04
_000_ 15.775
_001_ 39.47
_002_ 17.93
_003_ 27.45
_004_ 4.415
_005_ 13.24
_006_ 2.835
_007_ 6.6
_008_ 3.175
_009_ 10.78
_010_ 16.46
_011_ 15.335
_012_ 4.915
_013_ 6.735
_014_ 6.9
_015_ 6.18
_016_ 6.355
_017_ 2.52
_018_ 6.855
_019_ 6.2
_020_ 5.435
_021_ 2.835
_022_ 3.32
_023_ 16.555
_024_ 12.155
_025_ 7.3
_026_ 13.795
_027_ 10.32
_028_ 20.25
_029_ 5.555
_030_ 63.345
_031_ 22.535
_032_ 24.195
_033_ 4.095
_034_ 52.715
_035_ 18.41
_036_ 10.29
_037_ 10.775
_038_ 2.835
_039_ 18.175
_040_ 6.975
_041_ 10.12
_042_ 13.36
_043_ 4.555
_044_ 12.66
_045_ 4.6
_046_ 15.535
_047_ 6.5
_048_ 6.855
_049_ 5.435
_050_ 1.45
_051_ 20.675
_052_ 2.715
_053_ 13.235
_054_ 7.935
_055_ 8.835
_056_ 5.795
_057_ 5.555
_058_ 8.975
_059_ 12.075
_060_ 10.92
_061_ 11.12
_062_ 7.435
_063_ 13.44
_064_ 12.73
_065_ 3.175
_066_ 2.615
_067_ 3.975
_068_ 5.06
_069_ 4.51
_070_ 5.375
_071_ 20.795
_072_ 1.45
_073_ 5.375
_074_ 11.575
_075_ 5.895
_076_ 2.615
_077_ 8.595
_078_ 2.47
_088_ 3.755
_089_ 2.13
_090_ 2.955
_091_ 2.375
_092_ 8.275
_093_ 1.79
_094_ 3.295
_095_ 5.935
_096_ 3.755
_097_ 6.595
_098_ 2.035
_099_ 6.015
_100_ 3.875
_101_ 5.135
_102_ 5.255
_103_ 6.42
_104_ 8.9
_105_ 14.255
_106_ 4.795
_107_ 5.935
_108_ 13.635
_109_ 5.595
_110_ 5.595
_111_ 7.68
_112_ 6.76
_113_ 7.755
_114_ 6.175
_115_ 5.135
_116_ 7.98
_117_ 4.095
_118_ 11.915
_119_ 4.92
_120_ 7.64
_121_ 11.535
_122_ 9.575
_123_ 5.095
_124_ 7.275
_125_ 11.72
_126_ 4.6
_127_ 68.685
_128_ 122.47
_129_ 52.83
_130_ 31.2
_131_ 4.435
_132_ 6.355
_133_ 6.69
_134_ 3.32
_135_ 2.375
_136_ 29.935
_137_ 49.085
_138_ 46.275
_139_ 26.685
_140_ 2.375
_141_ 5.555
_142_ 30.6
_143_ 7.36
_144_ 9.08
_145_ 15.52
_146_ 2.18
_147_ 15.995
_148_ 2.18
_149_ 7.86
_150_ 13.96
_151_ 13.715
_152_ 11.675
_153_ 8.315
_154_ 2.18
_155_ 2.98
_156_ 3.68
_157_ 2.47
_158_ 3.105
_159_ 4.36
_160_ 2.865
_161_ 4.36
_162_ 3.56
_163_ 2.52
_164_ 2.79
_165_ 2.06
_166_ 2.865
_167_ 35.08
_168_ 1.72
_169_ 6.78
_170_ 2.64
_171_ 7.9
_172_ 2.3
_173_ 8.455
_174_ 3.995
_175_ 10.915
_176_ 8.915
_177_ 12.495
_178_ 3.295
_179_ 7.52
_180_ 6.055
_181_ 5.935
_182_ 9.655
_183_ 6.87
_184_ 9.455
_185_ 5.595
_186_ 6.735
_187_ 6.695
_188_ 5.78
_189_ 5.28
_190_ 1.84
_191_ 14.69
_192_ 3.68
_193_ 7.68
_194_ 2.375
_195_ 16.855
_196_ 2.375
_197_ 14.555
_198_ 2.18
_199_ 5.935
_200_ 3.855
clknet_0__037_ 47.695
clknet_0_divider.out 34.775
clknet_0_divider2.out 29.11
clknet_0_ext_clk 20.095
clknet_0_net10 15.86
clknet_0_pll_clk 25.185
clknet_0_pll_clk90 27.75
clknet_1_0__leaf__037_ 18.52
clknet_1_0__leaf_divider.out 30.195
clknet_1_0__leaf_divider2.out 39.5
clknet_1_0__leaf_ext_clk 7.675
clknet_1_0__leaf_pll_clk 133.48
clknet_1_0__leaf_pll_clk90 105.3
clknet_1_1__leaf__037_ 36.555
clknet_1_1__leaf_divider.out 30.49
clknet_1_1__leaf_divider2.out 30.985
clknet_1_1__leaf_ext_clk 10.9
clknet_1_1__leaf_net10 30.56
clknet_1_1__leaf_pll_clk 140.0
clknet_1_1__leaf_pll_clk90 81.725
divider.even_0.N\[0\] 37.4
divider.even_0.N\[1\] 59.265
divider.even_0.N\[2\] 49.23
divider.even_0.counter\[0\] 35.44
divider.even_0.counter\[1\] 21.945
divider.even_0.counter\[2\] 15.96
divider.even_0.out_counter 30.46
divider.odd_0.counter2\[0\] 45.395
divider.odd_0.counter2\[1\] 39.465
divider.odd_0.counter2\[2\] 35.43
divider.odd_0.counter\[0\] 58.335
divider.odd_0.counter\[1\] 76.265
divider.odd_0.counter\[2\] 54.365
divider.odd_0.initial_begin\[0\] 31.54
divider.odd_0.initial_begin\[1\] 34.305
divider.odd_0.initial_begin\[2\] 27.1
divider.odd_0.old_N\[0\] 12.12
divider.odd_0.old_N\[1\] 5.505
divider.odd_0.old_N\[2\] 8.12
divider.odd_0.out_counter 20.38
divider.odd_0.out_counter2 12.38
divider.odd_0.rst_pulse 13.455
divider.out 17.555
divider.syncNp\[0\] 9.74
divider.syncNp\[1\] 6.245
divider.syncNp\[2\] 13.14
divider2.even_0.N\[0\] 30.06
divider2.even_0.N\[1\] 74.42
divider2.even_0.N\[2\] 29.52
divider2.even_0.counter\[0\] 44.595
divider2.even_0.counter\[1\] 23.425
divider2.even_0.counter\[2\] 19.035
divider2.even_0.out_counter 37.805
divider2.odd_0.counter2\[0\] 51.04
divider2.odd_0.counter2\[1\] 34.33
divider2.odd_0.counter2\[2\] 22.58
divider2.odd_0.counter\[0\] 44.09
divider2.odd_0.counter\[1\] 64.815
divider2.odd_0.counter\[2\] 56.065
divider2.odd_0.initial_begin\[0\] 29.085
divider2.odd_0.initial_begin\[1\] 22.64
divider2.odd_0.initial_begin\[2\] 14.595
divider2.odd_0.old_N\[0\] 5.015
divider2.odd_0.old_N\[1\] 15.15
divider2.odd_0.old_N\[2\] 5.84
divider2.odd_0.out_counter 45.525
divider2.odd_0.out_counter2 24.295
divider2.odd_0.rst_pulse 8.625
divider2.out 21.46
divider2.syncNp\[0\] 7.3
divider2.syncNp\[1\] 2.85
divider2.syncNp\[2\] 10.9
ext_clk_syncd 5.335
ext_clk_syncd_pre 9.435
net1 41.16
net10 6.595
net11 20.7
net13 176.145
net14 136.48
net15 121.335
net16 59.205
net17 135.105
net18 186.43
net19 205.98
net2 26.44
net20 80.23
net21 90.58
net22 118.28
net23 93.17
net24 124.99
net25 114.165
net26 140.915
net27 136.565
net28 185.145
net29 129.47
net3 2.52
net30 8.32
net31 2.835
net32 2.715
net33 2.835
net34 3.54
net35 2.835
net36 1.84
net37 4.095
net38 6.815
net39 5.435
net4 48.26
net5 35.915
net6 39.32
net7 109.635
net8 83.1
net9 55.195
pll_clk_sel 60.08
reset_delay\[0\] 5.365
reset_delay\[1\] 3.405
reset_delay\[2\] 4.25
use_pll_first 41.655
use_pll_second 31.495
user_clk_buffered 7.98