mirror of https://github.com/efabless/caravel.git
80 lines
3.3 KiB
Makefile
80 lines
3.3 KiB
Makefile
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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PWDD := $(shell pwd)
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BLOCKS := $(shell basename $(PWDD))
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# ---- Include Partitioned Makefiles ----
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CONFIG = caravel_user_project
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# TestName = temp_partial
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# export COCOTB_ANSI_OUTPUT=0 # disable color in termianl
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export GUI=1
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export COCOTB_REDUCED_LOG_FMT=1
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# Change this line if you want to use existing cocotb test modules:
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# export PYTHONPATH := $(DESIGNS)/verilog/rtl/<your design python tests>
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# export LIBPYTHON_LOC=$(cocotb-config --libpython)
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#export VERILOG_PATH = ../../../
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#export CARAVEL_PATH = ../../../../../caravel/verilog/
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# include $(MCW_ROOT)/verilog/dv/make/env.makefile
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# #export VERILOG_PATH = ../../../
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# include $(MCW_ROOT)/verilog/dv/make/var.makefile
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# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
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# include $(MCW_ROOT)/verilog/dv/make/sim.makefile
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TESTCASE=$(TestName)
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MODULE=caravel_tests
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$(info $$MODULE is [$(MODULE)])
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cocotb:
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rm -rf sim_build/
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mkdir sim_build/
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# change project_tb.v to match your testbench
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#RTL
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iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
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-DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
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-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
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-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv
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#GL
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# iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
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# -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
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# -f$(VERILOG_PATH)/includes/includes.gl.caravel \
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# -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv
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#CVC
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# TESTCASE=$(TestName) MODULE=caravel_tests cvc64 +interp +acc+2 \
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# +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap\
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# +change_port_type +maxerrors 1\
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# +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY=#0 \
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# +define+TESTNAME=\"$(TestName)\" +define+RUNTAG=\"$(RUNTAG)\" +define+COCOTB_SIM=1\
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# -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
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# -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) -o sim_build/sim.vvp
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# verilator --vpi --public-flat-rw --prefix Vtop \
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# -LDFLAGS "-Wl,-rpath,$(cocotb-config --prefix)/cocotb/libs \
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# -L$(cocotb-config --prefix)/cocotb/libs \
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# -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils" \
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# $(cocotb-config --share)/lib/verilator/verilator.cpp\
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# -y $(VERILOG_PATH)/includes/includes.rtl.caravel \
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# -y $(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) --cc -o sim_build/sim.vvp caravel_top.sv
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# change this line to choose the comma separated test cases and the name of your python test module
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TESTCASE=$(TestName) MODULE=caravel_tests vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
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! grep failure results.xml
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