mirror of https://github.com/efabless/caravel.git
181 lines
5.8 KiB
C
181 lines
5.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <defs.h>
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#include <csr.h>
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// --------------------------------------------------------
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/*
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* SPI master Test
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* - Enables SPI master
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* - Uses SPI master to talk to external SPI module
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*/
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void spi_write(char c)
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{
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reg_spimaster_wdata = (unsigned long) c;
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// reg_spimaster_wdata = c;
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// spi_master_control_length_write(8);
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// spi_master_control_start_write(1);
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// reg_spimaster_control = 0x0800;
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reg_spimaster_control = 0x0801;
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}
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char spi_read()
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{
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// reg_spimaster_wdata = c;
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// spi_master_control_length_write(8);
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// spi_master_control_start_write(1);
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// reg_spimaster_control = 0x0800;
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// spi_write(0x00);
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// reg_spimaster_rdata = 0x00;
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// reg_spimaster_control = 0x0801;
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spi_write(0x00);
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while (reg_spimaster_status != 1);
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return reg_spimaster_rdata;
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}
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void main()
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{
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int i;
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uint32_t value;
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reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
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reg_debug_1 = 0x0;
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reg_debug_2 = 0x0;
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// For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4
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// should be outputs.
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reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI
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reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; // SDO
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reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; // CSB
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reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; // SCK
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/* Apply configuration */
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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reg_debug_2 =0xAA;
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reg_spi_enable = 1;
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// For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4
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// should be outputs.
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// Start test
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// Enable SPI master
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// SPI master configuration bits:
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// bits 7-0: Clock prescaler value (default 2)
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// bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
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// bit 9: CSB sense (0 = inverted, 1 = noninverted)
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// bit 10: SCK sense (0 = noninverted, 1 = inverted)
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// bit 11: mode (0 = read/write opposite edges, 1 = same edges)
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// bit 12: stream (1 = CSB ends transmission)
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// bit 13: enable (1 = enabled)
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// bit 14: IRQ enable (1 = enabled)
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// bit 15: (unused)
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reg_spimaster_cs = 0x10001; // sel=0, manual CS
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spi_write(0x03); // Write 0x03 (read mode)
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spi_write(0x00); // Write 0x00 (start address high byte)
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spi_write(0x00); // Write 0x00 (start address middle byte)
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spi_write(0x04); // Write 0x04 (start address low byte)
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value = spi_read(); // 0x93
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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value = spi_read(); // 0x01
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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value = spi_read(); // 0x00
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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reg_spimaster_cs = 0x0000; // release CS
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reg_spimaster_cs = 0x10001; // sel=0, manual CS
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spi_write(0x03); // Write 0x03 (read mode)
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spi_write(0x00); // Write 0x00 (start address high byte)
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spi_write(0x00); // Write 0x00 (start address middle byte)
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spi_write(0x08); // Write 0x08 (start address low byte)
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value = spi_read(); // 0x13
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if (value == 0x13)
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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value = spi_read(); // 0x02
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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reg_spimaster_cs = 0x0000; // release CS
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reg_spimaster_cs = 0x10001; // sel=0, manual CS
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spi_write(0x03); // Write 0x03 (read mode)
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spi_write(0x00); // Write 0x00 (start address high byte)
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spi_write(0x00); // Write 0x00 (start address middle byte)
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spi_write(0x0a); // Write 0x0a (start address low byte)
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value = spi_read(); // 0x63
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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value = spi_read(); // 0x57
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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value = spi_read(); // 0xb5
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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value = spi_read(); // 0x00
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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value = spi_read();// 0x23
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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value = spi_read(); // 0x20
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reg_debug_1 = value;
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// reg_debug_2 =0x55; // value is ready to be read
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// while (reg_debug_2 != 0xCC) // testbench has read the value
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reg_spimaster_cs = 0x0000; // release CS
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reg_spimaster_cs = 0x10001; // sel=0, manual CS
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}
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