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caravel
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1bc78c4eea
caravel
/
verilog
/
dv
/
cocotb
/
tests
/
spi_master
History
M0stafaRady
5e523bce5b
Add spi master temp created to simulate the silicon validation test and to be removed after
2022-10-04 10:46:34 -07:00
..
SPI_VIP.py
Add hk_regs_wr_wb_cpu test
2022-10-04 03:24:15 -07:00
spi_master.py
Add spi master temp created to simulate the silicon validation test and to be removed after
2022-10-04 10:46:34 -07:00
spi_master_rd.c
add new test spi_master_rd
2022-10-03 05:36:36 -07:00
spi_master_temp.c
Add spi master temp created to simulate the silicon validation test and to be removed after
2022-10-04 10:46:34 -07:00
test_data
add new test spi_master_rd
2022-10-03 05:36:36 -07:00