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caravel/lef/caravel_power_routing.lef

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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO caravel_power_routing
CLASS BLOCK ;
FOREIGN caravel_power_routing ;
ORIGIN 0.000 0.000 ;
SIZE 3588.000 BY 5188.000 ;
PIN vccd_core
PORT
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RECT 197.280 341.280 229.220 364.500 ;
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END
END vccd_core
PIN vssd_core
PORT
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LAYER met5 ;
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RECT 234.180 233.940 254.180 305.290 ;
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RECT 234.180 232.940 3248.340 233.940 ;
RECT 234.180 213.940 2956.980 232.940 ;
END
END vssd_core
PIN vccd2_core
PORT
LAYER met4 ;
RECT 306.910 1342.690 310.010 1379.380 ;
RECT 306.910 1339.590 326.260 1342.690 ;
RECT 323.160 1207.330 326.260 1339.590 ;
RECT 220.980 1192.330 326.260 1207.330 ;
RECT 974.410 1192.330 976.070 1207.320 ;
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RECT 220.980 1172.330 234.010 1192.330 ;
RECT 323.160 1192.000 326.260 1192.330 ;
RECT 3262.690 1191.330 3265.790 1379.380 ;
LAYER via4 ;
RECT 222.040 1173.135 232.820 1206.315 ;
RECT 282.830 1193.695 316.010 1206.075 ;
RECT 324.065 1205.650 325.245 1206.830 ;
RECT 324.065 1204.050 325.245 1205.230 ;
RECT 324.065 1202.450 325.245 1203.630 ;
RECT 324.065 1200.850 325.245 1202.030 ;
RECT 324.065 1199.250 325.245 1200.430 ;
RECT 324.065 1197.650 325.245 1198.830 ;
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RECT 324.065 1192.850 325.245 1194.030 ;
RECT 974.650 1205.685 975.830 1206.865 ;
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RECT 974.650 1194.485 975.830 1195.665 ;
RECT 974.650 1192.885 975.830 1194.065 ;
RECT 1025.250 1205.685 1026.430 1206.865 ;
RECT 1025.250 1204.085 1026.430 1205.265 ;
RECT 1025.250 1202.485 1026.430 1203.665 ;
RECT 1025.250 1200.885 1026.430 1202.065 ;
RECT 1025.250 1199.285 1026.430 1200.465 ;
RECT 1025.250 1197.685 1026.430 1198.865 ;
RECT 1025.250 1196.085 1026.430 1197.265 ;
RECT 1025.250 1194.485 1026.430 1195.665 ;
RECT 1025.250 1192.885 1026.430 1194.065 ;
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RECT 3263.605 1196.075 3264.785 1197.255 ;
RECT 3263.605 1194.475 3264.785 1195.655 ;
RECT 3263.605 1192.875 3264.785 1194.055 ;
LAYER met5 ;
RECT 221.270 1172.660 233.590 1206.790 ;
RECT 281.390 1192.330 3266.530 1207.330 ;
END
END vccd2_core
PIN vssd2_core
PORT
LAYER met4 ;
RECT 302.110 1337.890 305.210 1374.610 ;
RECT 302.110 1334.790 321.460 1337.890 ;
RECT 318.360 1227.330 321.460 1334.790 ;
RECT 204.920 1212.330 321.460 1227.330 ;
RECT 995.310 1212.330 996.970 1227.320 ;
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RECT 204.920 1191.330 218.060 1212.330 ;
RECT 318.360 1211.790 321.460 1212.330 ;
RECT 3267.490 1211.810 3270.590 1374.580 ;
LAYER via4 ;
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RECT 282.755 1213.525 315.935 1225.905 ;
RECT 319.315 1225.670 320.495 1226.850 ;
RECT 319.315 1224.070 320.495 1225.250 ;
RECT 319.315 1222.470 320.495 1223.650 ;
RECT 319.315 1220.870 320.495 1222.050 ;
RECT 319.315 1219.270 320.495 1220.450 ;
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RECT 319.315 1216.070 320.495 1217.250 ;
RECT 319.315 1214.470 320.495 1215.650 ;
RECT 319.315 1212.870 320.495 1214.050 ;
RECT 995.550 1225.685 996.730 1226.865 ;
RECT 995.550 1224.085 996.730 1225.265 ;
RECT 995.550 1222.485 996.730 1223.665 ;
RECT 995.550 1220.885 996.730 1222.065 ;
RECT 995.550 1219.285 996.730 1220.465 ;
RECT 995.550 1217.685 996.730 1218.865 ;
RECT 995.550 1216.085 996.730 1217.265 ;
RECT 995.550 1214.485 996.730 1215.665 ;
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RECT 3268.395 1224.085 3269.575 1225.265 ;
RECT 3268.395 1222.485 3269.575 1223.665 ;
RECT 3268.395 1220.885 3269.575 1222.065 ;
RECT 3268.395 1219.285 3269.575 1220.465 ;
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RECT 3268.395 1216.085 3269.575 1217.265 ;
RECT 3268.395 1214.485 3269.575 1215.665 ;
RECT 3268.395 1212.885 3269.575 1214.065 ;
LAYER met5 ;
RECT 205.330 1191.810 217.650 1226.940 ;
RECT 281.390 1212.330 3271.110 1227.330 ;
END
END vssd2_core
PIN vdda2_core
PORT
LAYER met3 ;
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RECT 199.620 2415.495 261.460 2439.395 ;
LAYER via3 ;
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LAYER met4 ;
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RECT 250.990 2415.470 261.110 2439.420 ;
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RECT 250.850 1272.330 307.060 1287.330 ;
RECT 303.960 1272.110 307.060 1272.330 ;
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LAYER via4 ;
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LAYER met5 ;
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END
END vdda2_core
PIN vssa2_core
PORT
LAYER met3 ;
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RECT 199.260 4138.495 250.010 4162.395 ;
LAYER via3 ;
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LAYER met4 ;
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LAYER via4 ;
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LAYER met5 ;
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END
END vssa2_core
PIN vssd1_core
PORT
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LAYER via3 ;
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LAYER met4 ;
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RECT 36.385 1032.590 43.070 1034.190 ;
RECT 36.385 1032.510 40.860 1032.590 ;
END
END vssd1_core
PIN vccd1_core
PORT
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RECT 30.425 1024.040 34.900 1024.140 ;
END
END vccd1_core
PIN vssa1_core
PORT
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LAYER met4 ;
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END
END vssa1_core
PIN vdda1_core
PORT
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END
END vdda1_core
OBS
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RECT 650.710 202.910 724.725 204.610 ;
END
END caravel_power_routing
END LIBRARY
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