caravel/signoff/digital_pll/final_summary_report.csv

1		design	design_name	config	flow_status	total_runtime	routed_runtime	(Cell/mm^2)/Core_Util	DIEAREA_mm^2	CellPer_mm^2	OpenDP_Util	Peak_Memory_Usage_MB	cell_count	tritonRoute_violations	Short_violations	MetSpc_violations	OffGrid_violations	MinHole_violations	Other_violations	Magic_violations	antenna_violations	lvs_total_errors	cvc_total_errors	klayout_violations	wire_length	vias	wns	pl_wns	optimized_wns	fastroute_wns	spef_wns	tns	pl_tns	optimized_tns	fastroute_tns	spef_tns	HPWL	routing_layer1_pct	routing_layer2_pct	routing_layer3_pct	routing_layer4_pct	routing_layer5_pct	routing_layer6_pct	wires_count	wire_bits	public_wires_count	public_wire_bits	memories_count	memory_bits	processes_count	cells_pre_abc	AND	DFF	NAND	NOR	OR	XOR	XNOR	MUX	inputs	outputs	level	EndCaps	TapCells	Diodes	Total_Physical_Cells	suggested_clock_frequency	suggested_clock_period	CLOCK_PERIOD	SYNTH_STRATEGY	SYNTH_MAX_FANOUT	FP_CORE_UTIL	FP_ASPECT_RATIO	FP_PDN_VPITCH	FP_PDN_HPITCH	PL_TARGET_DENSITY	GLB_RT_ADJUSTMENT	STD_CELL_LIBRARY	CELL_PAD	DIODE_INSERTION_STRATEGY
2	0	/home/ma/ef/caravel_openframe/openlane/digital_pll	digital_pll	digital_pll	flow completed	0h0m56s0ms	0h0m47s0ms	110933.33333333334	0.005625	55466.66666666667	81.42	551.6	312	0	0	0	0	0	0	0	0	0	0	-1	5632	2218	0.0	0.0	-1	0.0	-1	0.0	0.0	-1	0.0	-1	3849516.0	0.0	32.42	24.29	0.0	0.0	0.0	613	808	120	303	0	0	0	646	4	3	17	11	331	19	12	27	31	72	20	46	50	0	96	90.9090909090909	11.0	10.0	AREA 0	6	50	1	40	40	0.82	0	sky130_fd_sc_hd	0	4