mirror of https://github.com/efabless/caravel.git
23 lines
357 B
Verilog
23 lines
357 B
Verilog
module buff_flash_clkrst (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input[11:0] in_e,
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input[2:0] in_w,
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output[11:0] out_w,
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output[2:0] out_e);
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sky130_fd_sc_hd__clkbuf_8 BUF[14:0] (
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`ifdef USE_POWER_PINS
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.VGND(VGND),
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.VNB(VGND),
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.VPB(VPWR),
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.VPWR(VPWR)
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`endif
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.A({in_e, in_w}),
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.X({out_w, out_e})
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);
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endmodule
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