caravel/verilog
Tim Edwards 7bfab382d8 After updating from the PR that adds the gate level chip_io_openframe.v,
modified it so that it matches the modified chip_io_openframe layout
in this PR (namely, the GPIO "_wrapped" pads are replaced with the
equivalent non-wrapped base cells).
2023-09-25 20:10:37 -04:00
..
dv Update cocotb README file to include PDK export requirements 2022-10-30 01:47:46 -07:00
gl After updating from the PR that adds the gate level chip_io_openframe.v, 2023-09-25 20:10:37 -04:00
rtl Modified the openframe padframe so that the GPIO "wrapped" 2023-09-25 19:26:09 -04:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00