mirror of https://github.com/efabless/caravel.git
142 lines
4.0 KiB
ReStructuredText
Executable File
142 lines
4.0 KiB
ReStructuredText
Executable File
.. raw:: html
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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QSPI Flash interface
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====================
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Related pins
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------------
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* :ref:`flash_io[1:0] <flash_io>` - D9 and D10, respectively,
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* :ref:`flash_csb <flash_csb>` - C10,
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* :ref:`flash_clk <flash_clk>` - D8.
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Description
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-----------
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The QSPI flash controller is automatically enabled on power-up, and will
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immediately initiate a read sequence in single-bit mode
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with pin :ref:`flash_io0 <flash_io>` acting as ``SDI`` (data from flash to CPU)
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and pin :ref:`flash_io1 <flash_io>` acting as ``SDO`` (data from CPU to flash).
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Protocol is according to, e.g., `Cypress S25FL256L <https://www.cypress.com/file/316171/download>`_.
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The initial SPI instruction sequence is :ref:`as follows: <initial_spi_instruction_sequence>`.
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.. list-table:: Initial SPI instruction sequence
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:name: initial_spi_instruction_sequence
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:widths: auto
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* - ``0xFF``
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- Mode bit reset
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* - ``0xAB``
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- Release from deep power-down
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* - ``0x03``
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- Read w/3 byte address
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* - ``0x00``
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- Program start address (``0x10000000``) (3 bytes) (upper byte is ignored)
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* - ``0x00``
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-
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* - ``0x00``
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-
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The QSPI flash continues to read bytes, either sequentially on the same command,
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or issuing a new read command to read from a new address.
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.. _reg_spictrl:
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``reg_spictrl``
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---------------
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**QSPI control register**
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The behaviour of the QSPI flash controller can be modified by changing values in the register below:
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Base address: ``0x2d000000``
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.. wavedrom::
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{ "reg": [
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{"name": "FLASH_IO[3:0]", "bits": 4},
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{"name": "CLK", "bits": 1},
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{"name": "CSB", "bits": 1},
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{"bits": 2, "type": 1},
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{"name": "OE_FLASH_IO [3:0]", "bits": 4},
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{"bits": 4, "type": 1},
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{"name": "DUMMY CLK COUNT", "bits": 4},
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{"name": "ACCESS MODE", "bits": 3},
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{"bits": 8, "type": 1},
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{"name": "EN", "bits": 1}],
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"config": {"hspace": 1400}
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}
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.. list-table:: ``reg_spictrl`` register description
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:name: reg_spictrl_description
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:header-rows: 1
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:widths: auto
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* - Mask bit
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- Default
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- Description
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* - 31
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- 1
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- QSPI flash interface enable
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* - 22-20
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- 0
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- Access mode *(including DDR enable, QSPI enable, CRM enable)* (see :ref:`reg_spictrl_access_mode_values`)
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* - 19-16
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- 8
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- Dummy clock cycle count / Read latency cycles
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* - 11-8
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- 0
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- Bit-bang ``OE_FLASH_IO[3:0]`` I/O output enable
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* - 5
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- 0
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- Bit-bang ``FLASH_CSB`` chip select bit
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* - 4
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- 0
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- Bit-bang ``FLASH_CLK`` serial clock line
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* - 3-0
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- 0
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- Bit-bang ``FLASH_IO[3:0]`` data bits
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QSPI access modes
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-----------------
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.. list-table:: ``reg_spictrl`` Access mode bit values
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:name: reg_spictrl_access_mode_values
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:widths: auto
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* - 0
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- ``000``
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- Single bit per clock
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* - 1
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- ``001``
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- Single bit per clock (same as 0)
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All additional modes (QSPI dual and quad modes) cannot be used,
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as the management SoC only has pins for data lines 0 and 1.
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The SPI flash can be accessed by bit banging when the enable is off.
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To do this from the CPU, the entire routine to access the SPI flash
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must be read into SRAM and executed from the SRAM.
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.. note::
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To sum up, the DDR enable, QSPI enable and CRM enable bits cannot be used due to the limited number of data pins.
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