mirror of https://github.com/efabless/caravel.git
126 lines
4.4 KiB
ReStructuredText
Executable File
126 lines
4.4 KiB
ReStructuredText
Executable File
.. raw:: html
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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Memory Mapped I/O summary
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=========================
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.. list-table:: Memory mapped I/O summary by address
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:name: memory_mapped_io_summary_by_address
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:header-rows: 1
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:widths: auto
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* - Address (bytes)
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- Function
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* - `0x 00 00 00 00`
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- Flash SPI / overlaid SRAM (4k words) start of memory block
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* - `0x 00 00 3f ff`
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- End of SRAM
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* - `0x 10 00 00 00`
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- Flash SPI start of program block.
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Program to run starts here on reset
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(see :ref:`SPI Flash initialization <initial_spi_instruction_sequence>`).
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* - `0x 10 ff ff ff`
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- Maximum SPI flash addressable space (16MB) with QSPI 3-byte addressing
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* - `0x 1f ff ff ff`
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- Maximum SPI flash addressable space (32MB)
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* - `0x 20 00 00 00`
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- UART clock divider select (:ref:`reg_uart_clkdiv`)
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* - `0x 20 00 00 04`
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- UART data (:ref:`reg_uart_data`)
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* - `0x 20 00 00 08`
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- UART enable (:ref:`reg_uart_enable`)
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* - `0x 21 00 00 00`
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- GPIO input/output (bit 16/bit 0) (:ref:`reg_gpio_data`). 1 general-purpose digital, management area only.
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* - `0x 21 00 00 04`
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- GPIO output enable (:ref:`reg_gpio_ena`)
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* - `0x 21 00 00 08`
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- GPIO pullup enable (:ref:`reg_gpio_pu`)
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* - `0x 21 00 00 0c`
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- GPIO pulldown enable (:ref:`reg_gpio_pd`)
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* - `0x 22 00 00 00`
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- Counter/Timer 0 configuration register (:ref:`reg_timer0_config`)
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* - `0x 22 00 00 04`
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- Counter/Timer 0 current value (:ref:`reg_timer0_value`)
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* - `0x 22 00 00 08`
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- Counter/Timer 0 reset value (:ref:`reg_timer0_data`)
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* - `0x 23 00 00 00`
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- Counter/Timer 1 configuration register (:ref:`reg_timer1_config`)
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* - `0x 23 00 00 04`
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- Counter/Timer 1 current value (:ref:`reg_timer1_value`)
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* - `0x 23 00 00 08`
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- Counter/Timer 1 reset value (:ref:`reg_timer1_data`)
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* - `0x 24 00 00 00`
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- SPI controller configuration register (:ref:`reg_spi_config`)
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* - `0x 24 00 00 08`
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- SPI controller data register (:ref:`reg_spi_data`)
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* - `0x 25 00 00 00`
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- Logic Analyzer Data 0
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* - `0x 25 00 00 04`
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- Logic Analyzer Data 1
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* - `0x 25 00 00 08`
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- Logic Analyzer Data 2
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* - `0x 25 00 00 0c`
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- Logic Analyzer Data 3
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* - `0x 25 00 00 10`
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- Logic Analyzer Enable 0
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* - `0x 25 00 00 14`
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- Logic Analyzer Enable 1
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* - `0x 25 00 00 18`
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- Logic Analyzer Enable 2
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* - `0x 25 00 00 1c`
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- Logic Analyzer Enable 3
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* - `0x 26 00 00 00`
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- User project area GPIO data (L)
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* - `0x 26 00 00 04`
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- User project area GPIO data (H)
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* - `0x 26 00 00 08`
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- User project area GPIO data transfer (bit 0, auto-zeroing)
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* - `0x 26 00 00 0c`
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- User project area GPIO ``mprj_io[0]`` configure
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* - ...
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- ...
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* - `0x 26 00 00 a0`
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- User project area GPIO ``mprj_io[37]`` configure
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* - `0x 26 00 00 a4`
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- User project area GPIO power[0] configure (currently undefined/unused)
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* - ...
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- ...
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* - `0x 26 00 00 b4`
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- User project area GPIO power[3] configure (currently undefined/unused)
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* - `0x 2d 00 00 00`
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- QSPI controller config (:ref:`reg_spictrl`)
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* - `0x 2f 00 00 00`
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- PLL clock output destination (:ref:`reg_pll_out_dest`)
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* - `0x 2f 00 00 04`
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- Trap output destination (:ref:`reg_trap_out_dest`)
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* - `0x 2f 00 00 08`
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- IRQ 7 input source (:ref:`reg_irq7_source`)
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* - `0x 30 00 00 00`
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- User area base.
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A user project may define additional Wishbone responder modules starting at this address.
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* - `0x 80 00 00 00`
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- QSPI controller
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* - `0x 90 00 00 00`
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- :ref:`storage-area-sram`
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* - `0x a0 00 00 00`
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- Any responder 1
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* - `0x b0 00 00 00`
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- Any responder 2
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