caravel/verilog
Tim Edwards 1035e8b469 Updated caravel and caravan layouts to reflect the simple change
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core.  Also:  Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
2021-11-30 10:05:43 -05:00
..
dv Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
gl [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
rtl Updated caravel and caravan layouts to reflect the simple change 2021-11-30 10:05:43 -05:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00