caravel/verilog
M0stafaRady 0f0a495906 merge with caravel_redesign 2022-10-10 05:04:44 -07:00
..
dv move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
gl added constant_block view 2022-10-08 12:05:53 -07:00
rtl merge with caravel_redesign 2022-10-10 05:04:44 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00