caravel/verilog
passant5 0c9e3a08fd
update caravel with tying `porb_h_in` with `por_l_in` (#326)
* update caravel with tying `porb_h_in` with `por_l_in` at the `mgmt_core_wrapper` in the top-level layout:
- `porb_h_in` shouldn't be left floating as it is an input to `clkbuf_16`

* add caravel-eco.gds (same as caravel.gds)
2022-10-21 11:52:00 -07:00
..
dv cocotb - updates related to enable simulating caraval using iverilog (#320) 2022-10-21 07:43:34 -07:00
gl update caravel with tying `porb_h_in` with `por_l_in` (#326) 2022-10-21 11:52:00 -07:00
rtl Syntax changes that are non-functional from a synthesis perspective. (#324) 2022-10-21 10:10:20 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00